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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
D Highest-Performance Floating-Point Digital
Signal Processor (DSP): TMS320C6713 - Eight 32-Bit Instructions/Cycle - 32/64-Bit Data Word - 225-, 150-MHz Clock Rate - 4.4-, 6.7-ns Instruction Cycle Time - 1800 MIPS/1350 MFLOPS, 1200 MIPS /900 MFLOPS - Rich Peripheral Set, Optimized for Audio VelociTI Advanced Very Long Instruction Word (VLIW) TMS320C67x DSP Core - Eight Independent Functional Units: - Two ALUs (Fixed-Point) - Four ALUs (Floating- and Fixed-Point) - Two Multipliers (Floating- and Fixed-Point) - Load-Store Architecture With 32 32-Bit General-Purpose Registers - Instruction Packing Reduces Code Size - All Instructions Conditional Instruction Set Features - Native Instructions for IEEE 754 - Single- and Double-Precision - Byte-Addressable (8-, 16-, 32-Bit Data) - 8-Bit Overflow Protection - Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization L1/L2 Memory Architecture - 4K-Byte L1P Program Cache (Direct-Mapped) - 4K-Byte L1D Data Cache (2-Way) - 256K-Byte L2 Memory, With 64K-Byte L2 Unified Cache/Mapped RAM - 192K-Byte Additional L2 Mapped RAM Device Configuration - Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot - Endianness: Little Endian, Big Endian 32-Bit External Memory Interface (EMIF) - Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM - 512M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
D 16-Bit Host-Port Interface (HPI) D Two Multichannel Audio Serial Ports
(McASPs) - Two Independent Clock Zones Each (1 TX and 1 RX) - Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones - Each Clock Zone Includes: - Programmable Clock Generator - Programmable Frame Sync Generator - TDM Streams From 2-32 Time Slots - Support for Slot Size: 8, 12, 16, 20, 24, 28, 32 Bits - Data Formatter for Bit Manipulation - Wide Variety of I2S and Similar Bit Stream Formats - Integrated Digital Audio Interface Transmitter (DIT) Supports: - S/PDIF, IEC60958-1, AES-3 Formats - Up to 16 transmit pins - Enhanced Channel Status/User Data RAM - Extensive Error Checking and Recovery Two Inter-Integrated Circuit (I2C) Buses Multi-Master and Slave Interfaces Two Multichannel Buffered Serial Ports (McBSPs): - Serial-Peripheral-Interface (SPI) - High-Speed TDM Interface - AC97 Interface Two 32-Bit General-Purpose Timers One Dedicated General-Purpose Input/Output Module With 16 pins Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module IEEE-1149.1 (JTAG) Boundary-Scan-Compatible Package Options: - 208-Pin PowerPAD Plastic (Low-Profile) Quad Flatpack (PYP) - 256-Pin Ball Grid Array Package (GFN) 0.13-m/6-Level Metal Process - CMOS Technology 3.3-V I/Os, 1.2-V Internal
D
D
D D
D
D D D D D
D
D
D
D D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C67x, VelociTI, and PowerPAD are trademarks of Texas Instruments. All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright 2001, Texas Instruments Incorporated
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PRODUCT PREVIEW
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
Table of Contents
PYP PowerPAD QFP package (top view) . . . . . . . . . . . . . . 3 GFN BGA package (bottom view) . . . . . . . . . . . . . . . . . . . . . . 3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional block and CPU (DSP core) diagram . . . . . . . . . . . 6 CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . . 7 memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 11 PWRD bits in CPU CSR register description . . . . . . . . . . . 19 interrupts and interrupt selector . . . . . . . . . . . . . . . . . . . . . . . 20 EDMA module and EDMA selector . . . . . . . . . . . . . . . . . . . . 21 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 clock generator, oscillator, and PLL . . . . . . . . . . . . . . . . . . . 61 absolute maximum ratings over operating case temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 recommended operating conditions . . . . . . . . . . . . . . . . . . . 67 electrical characteristics over recommended ranges of supply voltage and operating case temperature . 68 parameter measurement information . . . . . . . . . . . . . . . 69 signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 timing parameters and board routing analysis . . . . . . . 70 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 75 synchronous-burst memory timing . . . . . . . . . . . . . . . . . 78 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 80 HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 90 multichannel audio serial port (McASP) timing . . . . . . . 91 inter-integrated circuits (I2C) timing . . . . . . . . . . . . . . . . 94 host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 95 multichannel buffered serial port timing . . . . . . . . . . . . . 98 timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 general-purpose input/output (GPIO) port timing . . . . 110 JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
PYP PowerPAD QFP package (top view)
PYP 208-PIN PowerPAD PLASTIC QUAD FLATPACK (PQFP) ( TOP VIEW ) 156 105
157
104
208
53
1
52
GFN BGA package (bottom view)
GFN 256-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW )
Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
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PRODUCT PREVIEW
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
description
The TMS320C67xt DSPs (including the TMS320C6713 device) compose the floating-point DSP generation in the TMS320C6000t DSP platform. The TMS320C6713 (C6713) device is based on the high-performance, advanced VelociTIt very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. Operating at 225 MHz, the C6713 delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS). The C6713 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-Byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-Byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-Byte memory space that is shared between program and data space. 64K Bytes of the 256K Bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K Bytes in L2 serves as mapped SRAM. The C6713 has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713 has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The two I2C ports on the TMS320C6713 allow the DSP to easily control peripheral devices, boot from a serial EEPROM, and communicate with a host processor. The TMS320C67x DSP generation is supported by the TI eXpressDSPt set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studiot Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOSt kernel.
PRODUCT PREVIEW
TMS320C6000, eXpressDSP, Code Composer Studio, and DSP/BIOS are trademarks of Texas Instruments.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
device characteristics
Table 1 provides an overview of the C6713 DSP. The table shows significant features of the C6713 device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C67x DSP device part numbers and part numbering, see Table 32 and Figure 11. Table 1. Characteristics of the C6713 Processor
HARDWARE FEATURES GFN EMIF EDMA (16 Channels) HPI (16 bit) McASPs Peripherals I2Cs McBSPs 32-Bit Timers GPIO Modules Size (Bytes) On-Chip Memory 1 (32 bit) 1 1 2 2 2 2 264K 4K-Byte (4KB) L1 Program (L1P) Cache 4KB L1 Data (L1D) Cache 64KB Unified L2 Cache/Mapped RAM 192KB L2 Mapped RAM 0x0203 225, 150 4.4 ns (C6713GFN-225), 6.7 ns (C6713GFN-150) 1.2 3.3 /1, /2, /3, ..., /32 x1, x2, x3, ..., x16 /1, /2, /3, ..., /32 256-Pin BGA (GFN) - 0.13 - 208-Pin PowerPAD PQFP (PYP) 150 6.7 ns (C6713PYP-150) 1 C6713 (FLOATING-POINT DSP) PYP 1 (16 bit)
Organization
CPU ID+CPU Rev ID Frequency Cycle Time Voltage
Control Status Register (CSR.[31:16]) MHz ns Core (V) I/O (V) Prescaler Multiplier Postscaler 27 x 27 mm
Clock Generator Options
Packages Process Technology Product Status Product Preview (PP) Advance Information (AI) Production Data (PD)
28 x 28 mm m
PP
PP
C67x is a trademark of Texas Instruments.
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PRODUCT PREVIEW
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
functional block and CPU (DSP core) diagram
C6713 Digital Signal Processor
32 EMIF L1P Cache Direct Mapped 4K Bytes Total
McASP1
L2 Cache/ Memory 4 Banks 64K Bytes Total (up to 4-Way)
C67x CPU Instruction Fetch Instruction Dispatch Control Registers Control Logic Test In-Circuit Emulation Interrupt Control
McASP0
McBSP1
Instruction Decode Data Path A Data Path B B Register File
Pin Multiplexing
McBSP0
A Register File
I2C1
PRODUCT PREVIEW
Enhanced DMA Controller (16 channel) L2 Memory 192K Bytes
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
I2C0
Timer 1
L1D Cache 2-Way Set Associative 4K Bytes
Timer 0
Clock Generator, Oscillator, and PLL x1 through x16 Multipliers
Power-Down Logic
GPIO
16
HPI
In addition to fixed-point instructions, these functional units execute floating-point instructions. EMIF interfaces to: -SDRAM -SBSRAM -SRAM, -ROM/Flash, and -I/O devices McBSPs interface to: -SPI Control Port -High-Speed TDM Codecs -AC97 Codecs -Serial EEPROM McASPs interface to: -I2S Multichannel ADC, DAC, Codec, DIR -DIT: Multiple Outputs
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
CPU (DSP core) description
The TMS320C6713 floating-point digital signal processor is based on the C67x CPU. The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically "true"). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.
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PRODUCT PREVIEW
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
CPU (DSP core) description (continued)
src1
.L1 src2
dst long dst long src
8
8
LD1 32 MSB ST1
32 32
Data Path A
long src long dst dst .S1 src1 src2
8
8
dst src1 .M1 src2
LD1 32 LSB
DA1
.D1
dst src1 src2
DA2
.D2
src2 src1 dst
LD2 32 LSB
src2
.M2 src1 dst src2
Data Path B
src1 .S2 dst long dst long src
8
8
In addition to fixed-point instructions, these functional units execute floating-point instructions.
Figure 1. TMS320C67x CPU (DSP Core) Data Paths
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AA AA
LD2 32 MSB ST2
32 32
long src long dst dst .L2 src2
8
8
src1
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A AAAAA AAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAA A AAAAAA AAAAAA AAAAA AAAAA AAAAA AAAAA AAAAA A AAAAAA AAAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAA AAAAAA AAAAA AAAAAA AAAAA AAAAA AAAAA
Register File A (A0-A15) 2X 1X Register File B (B0-B15) Control Register File
AA A A AA A AAAA A AA A AAAA AA AAAAA AA AAAAA AAAAA AAAAA A AAAA A A AAAA A AAAAA AA A AAAA A AA A AA A AAAA A AAAA A AA A AAAA A AA A AAAA A AAAAA A AAAA A A AAAA A A AAAA A A AAAA A AAAAA AA A A AA A AAAA A AAAA A A AAAA A AA A AAAA AAAAA A AA A AAAA A AAAAA A AAAA A A AAAA A A A A AAAA A AA AAAAA AA AAAAA AA A AAAA AA AAAAA AA A AAAA A
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AA AA AA AA
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
memory map summary
Table 2 shows the memory map address ranges of the C6713 device. Table 2. TMS320C6713 Memory Map Summary
MEMORY BLOCK DESCRIPTION Internal RAM (L2) Internal RAM/Cache Reserved External Memory Interface (EMIF) Registers L2 Registers Reserved HPI Registers McBSP 0 Registers McBSP 1 Registers Timer 0 Registers Timer 1 Registers Interrupt Selector Registers Device Configuration Registers Reserved EDMA RAM and EDMA Registers Reserved GPIO Registers Reserved I2C0 Registers I2C1 Registers Reserved McASP0 Registers McASP1 Registers Reserved PLL Registers Reserved QDMA Registers Reserved Reserved McBSP0 Data McBSP1 Data Reserved McASP0 Data McASP1 Data Reserved EMIF CE0 EMIF CE1 EMIF CE2 EMIF CE3 Reserved BLOCK SIZE (BYTES) 192K 64K 24M - 256K 256K 128K 128K 256K 256K 256K 256K 256K 512 4 256K - 516 256K 768K 16K 240K 16K 16K 16K 16K 16K 160K 8K 4M + 520K 52 16M - 52 720M 64M 64M 64M 1M 1M 1G + 62M 256M 256M 256M 256M 1G HEX ADDRESS RANGE 0000 0000 - 0002 FFFF 0003 0000 - 0003 FFFF 0004 0000 - 017F FFFF 0180 0000 - 0183 FFFF 0184 0000 - 0185 FFFF 0186 0000 - 0187 FFFF 0188 0000 - 018B FFFF 018C 0000 - 018F FFFF 0190 0000 - 0193 FFFF 0194 0000 - 0197 FFFF 0198 0000 - 019B FFFF 019C 0000 - 019C 01FF 019C 0200 - 019C 0203 01A0 0000 - 01A3 FFFF 01A4 0000 - 01AF FFFF 01B0 0000 - 01B0 3FFF 01B0 4000 - 01B3 FFFF 01B4 0000 - 01B4 3FFF 01B4 4000 - 01B4 7FFF 01B4 8000 - 01B4 BFFF 01B4 C000 - 01B4 FFFF 01B5 0000 - 01B5 3FFF 01B5 4000 - 01B7 BFFF 01B7 C000 - 01B7 DFFF 01B7 E000 - 01FF FFFF 0200 0000 - 0200 0033 0200 0034 - 02FF FFFF 0300 0000 - 2FFF FFFF 3000 0000 - 33FF FFFF 3400 0000 - 37FF FFFF 3800 0000 - 3BFF FFFF 3C00 0000 - 3C0F FFFF 3C10 0000 - 3C1F FFFF 3C20 0000 - 7FFF FFFF 8000 0000 - 8FFF FFFF 9000 0000 - 9FFF FFFF A000 0000 - AFFF FFFF B000 0000 - BFFF FFFF C000 0000 - FFFF FFFF 019C 0204 - 019F FFFF
The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
L2 memory structure expanded Figure 2 shows the detail of the L2 memory structure.
L2 Mode 000 001 010 011 111 0x0000 0000 L2 Memory Block Base Address
208K SRAM
192K SRAM
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256K SRAM (All)
240KSRAM
224K SRAM
192 K Bytes
0x0003 0000
64K 4-Way Cache
48K 3-Way Cache
32K 2-Way Cache
16K 1-Way Cache
Figure 2. L2 Memory Configuration
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IIIIIIIIII IIIIIIIIII IIIIIIIIII
16 K Bytes 16 K Bytes 16 K Bytes 16 K Bytes
0x0003 4000 0x0003 8000 0x0003 C000 0x0003 FFFF
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
peripheral register descriptions
Table 3 through Table 13 identify the peripheral registers for the C6713 device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names, and their descriptions, see the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table 3. EMIF Registers
HEX ADDRESS RANGE 0180 0000 0180 0004 0180 0008 0180 000C 0180 0010 0180 0014 0180 0018 0180 001C 0180 0020 0180 0024 - 0183 FFFF ACRONYM GBLCTL CECTL1 CECTL0 - CECTL2 CECTL3 SDCTL SDTIM SDEXT - EMIF global control EMIF CE1 space control EMIF CE0 space control Reserved EMIF CE2 space control EMIF CE3 space control EMIF SDRAM control EMIF SDRAM refresh control EMIF SDRAM extension Reserved REGISTER NAME
Table 4. L2 Cache Registers
HEX ADDRESS RANGE 0184 0000 0184 4000 0184 4004 0184 4010 0184 4014 0184 4020 0184 4024 0184 4030 0184 4034 0184 5000 0184 5004 0184 8200 0184 8204 0184 8208 0184 820C 0184 8240 0184 8244 0184 8248 0184 824C 0184 8280 0184 8284 0184 8288 0184 828C 0184 82C0 0184 82C4 0184 82C8 0184 82CC 0184 82D0 - 0185 FFFF ACRONYM CCFG L2FBAR L2FWC L2CBAR L2CWC L1PFBAR L1PFWC L1DFBAR L1DFWC L2FLUSH L2CLEAN MAR0 MAR1 MAR2 MAR3 MAR4 MAR5 MAR6 MAR7 MAR8 MAR9 MAR10 MAR11 MAR12 MAR13 MAR14 MAR15 - Cache configuration register L2 flush base address register L2 flush word count register L2 clean base address register L2 clean word count register L1P flush base address register L1P flush word count register L1D flush base address register L1D flush word count register L2 flush register L2 clean register Controls CE0 range 8000 0000 - 80FF FFFF Controls CE0 range 8100 0000 - 81FF FFFF Controls CE0 range 8200 0000 - 82FF FFFF Controls CE0 range 8300 0000 - 83FF FFFF Controls CE1 range 9000 0000 - 90FF FFFF Controls CE1 range 9100 0000 - 91FF FFFF Controls CE1 range 9200 0000 - 92FF FFFF Controls CE1 range 9300 0000 - 93FF FFFF Controls CE2 range A000 0000 - A0FF FFFF Controls CE2 range A100 0000 - A1FF FFFF Controls CE2 range A200 0000 - A2FF FFFF Controls CE2 range A300 0000 - A3FF FFFF Controls CE3 range B000 0000 - B0FF FFFF Controls CE3 range B100 0000 - B1FF FFFF Controls CE3 range B200 0000 - B2FF FFFF Controls CE3 range B300 0000 - B3FF FFFF Reserved REGISTER NAME
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
peripheral register descriptions (continued)
Table 5. Interrupt Selector Registers
HEX ADDRESS RANGE 019C 0000 019C 0004 019C 0008 019C 000C - 019F FFFF ACRONYM MUXH MUXL EXTPOL - REGISTER NAME Interrupt multiplexer high Interrupt multiplexer low External interrupt polarity Reserved COMMENTS Selects which interrupts drive CPU interrupts 10-15 (INT10-INT15) Selects which interrupts drive CPU interrupts 4-9 (INT04-INT09) Sets the polarity of the external interrupts (EXT_INT4-EXT_INT7)
Table 6. EDMA Parameter RAM
HEX ADDRESS RANGE 01A0 0000 - 01A0 0017 01A0 0018 - 01A0 002F 01A0 0030 - 01A0 0047 ACRONYM - - - - - - - - - - - - - - - - - - - - Parameters for Event 0 (6 words) Parameters for Event 1 (6 words) Parameters for Event 2 (6 words) Parameters for Event 3 (6 words) Parameters for Event 4 (6 words) Parameters for Event 5 (6 words) Parameters for Event 6 (6 words) Parameters for Event 7 (6 words) Parameters for Event 8 (6 words) Parameters for Event 9 (6 words) Parameters for Event 10 (6 words) Parameters for Event 11 (6 words) Parameters for Event 12 (6 words) Parameters for Event 13 (6 words) Parameters for Event 14 (6 words) Parameters for Event 15 (6 words) Reload/link parameters for Event M (6 words) Reload/link parameters for Event N (6 words) ... Reload/link parameters for Event Z (6 words) REGISTER NAME
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01A0 0048 - 01A0 005F 01A0 0060 - 01A0 0077 01A0 0078 - 01A0 008F 01A0 0090 - 01A0 00A7 01A0 00A8 - 01A0 00BF 01A0 00C0 - 01A0 00D7 01A0 00D8 - 01A0 00EF 01A0 00F0 - 01A0 00107 01A0 0108 - 01A0 011F 01A0 0120 - 01A0 0137 01A0 0138 - 01A0 014F 01A0 0150 - 01A0 0167 01A0 0168 - 01A0 017F 01A0 0180 - 01A0 0197 01A0 0198 - 01A0 01AF ... 01A0 07E0 - 01A0 07F7 01A0 07F8 - 01A0 07FF
Scratch pad area (2 words) The C6211/C6211B device has sixty-nine parameter sets [six (6) words each] that can be used to reload/link EDMA transfers.
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peripheral register descriptions (continued)
Table 7. EDMA Registers
HEX ADDRESS RANGE 01A0 0800 - 01A0 FEFC 01A0 FF00 01A0 FF04 01A0 FF08 01A0 FF0C 01A0 FF1F - 01A0 FFDC 01A0 FFE0 01A0 FFE4 01A0 FFE8 01A0 FFEC 01A0 FFF0 01A0 FFF4 01A0 FFF8 01A0 FFFC 01A1 0000 - 01A3 FFFF ACRONYM - ESEL0 ESEL1 - ESEL3 - PQSR CIPR CIER CCER ER EER ECR ESR - Reserved EDMA event selector 0 EDMA event selector 1 Reserved EDMA event selector 3 Reserved Priority queue status register Channel interrupt pending register Channel interrupt enable register Channel chain enable register Event register Event enable register Event clear register Event set register Reserved REGISTER NAME
Table 8. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE 0200 0000 0200 0004 0200 0008 0200 000C 0200 0010 0200 0014 - 0200 001C 0200 0020 0200 0024 0200 0028 0200 002C 0200 0030 ACRONYM QOPT QSRC QCNT QDST QIDX - QSOPT QSSRC QSCNT QSDST QSIDX QDMA options parameter register QDMA source address register QDMA frame count register QDMA destination address register QDMA index register Reserved QDMA pseudo options register QDMA pseudo source address register QDMA pseudo frame count register QDMA pseudo destination address register REGISTER NAME
QDMA pseudo index register All the QDMA and Pseudo registers are write-accessible only
Table 9. PLL Wrapper Registers
HEX ADDRESS RANGE 01B7 C000 - 01B7 C0FF 01B7 C100 01B7 C104 - 01B7 C10F 01B7 C110 01B7 C114 01B7 C118 01B7 C11C 01B7 C120 01B7 C124 01B7 C128 - 01B7 DFFF ACRONYM - PLLCSR - PLLM PLLDIV0 PLLDIV1 PLLDIV2 PLLDIV3 OSCDIV1 - Reserved PLL control/status register Reserved PLL multiplier control register PLL wrapper divider 0 register PLL wrapper divider 1 register PLL wrapper divider 2 register PLL wrapper divider 3 register Oscillator divider 1 register Reserved REGISTER NAME
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
peripheral register descriptions (continued)
Table 10. McASP0 and McASP1 Registers
HEX ADDRESS RANGE McASP0 01B4 C000 01B4 C004 01B4 C008 01B4 C00C 01B4 C010 01B4 C014 01B4 C018 01B4 C01C 01B4 C020 01B4 C024 - 01B4 C040 01B4 C044 01B4 C048 01B4 C04C 01B4 C050 01B4 C054 - 01B4 C05C 01B4 C060 01B4 C064 01B4 C068 01B4 C06C 01B4 C070 01B4 C074 01B4 C078 01B4 C07C 01B4 C080 01B4 C084 01B4 C088 01B4 C08C - 01B4 C09C 01B4 C0A0 01B4 C0A4 01B4 C0A8 01B4 C0AC 01B4 C0B0 01B4 C0B4 01B4 C0B8 01B4 C0BC 01B4 C0C0 01B4 C0C4 McASP1 01B5 0000 01B5 0004 01B5 0008 01B5 000C 01B5 0010 01B5 0014 01B5 0018 01B5 001C 01B5 0020 01B5 0024 - 01B5 0040 01B5 0044 01B5 0048 01B5 004C 01B5 0050 01B5 0054 - 01B5 005C 01B5 0060 01B5 0064 01B5 0068 01B5 006C 01B5 0070 01B5 0074 01B5 0078 01B5 007C 01B5 0080 01B5 0084 01B5 0088 01B5 008C - 01B5 009C 01B5 00A0 01B5 00A4 01B5 00A8 01B5 00AC 01B5 00B0 01B5 00B4 01B5 00B8 01B5 00BC 01B5 00C0 01B5 00C4 ACRONYM - PWRDEMU - - PFUNC PDIR PDOUT PDIN/PDSET PDCLR - GBLCTL AMUTE DLBCTL DITCTL - RGBLCTL RMASK RFMT AFSRCTL ACLKRCTL AHCLKRCTL RTDM RINTCTL RSTAT RSLOT RCLKCHK - XGBLCT XMASK XFMT AFSXCTL ACLKXCTL AHCLKXCTL XTDM XINTCTL XSTAT XSLOT Reserved Power down and emulation management register Reserved Reserved Pin function register Pin direction register Pin data out register Pin data in / data set register Read returns: PDIN Writes affect: PDSET Pin data clear register Reserved Global control register Mute control register Digital Loop-back control register DIT mode control register Reserved Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset independently from receive. Receiver format unit bit mask register Receive bit stream format register Receive frame sync control register Receive clock control register High-frequency receive clock control register Receive TDM slot 0-31 register Receiver interrupt control register Status register - Receiver Current receive TDM slot register Receiver clock check control register Reserved Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset independently from receive. Transmit format unit bit mask register Transmit bit stream format register Transmit frame sync control register Transmit clock control register High-frequency Transmit clock control register Transmit TDM slot 0-31 register Transmit interrupt control register Status register - Transmitter Current transmit TDM slot REGISTER NAME
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peripheral register descriptions (continued)
Table 10. McASP0 and McASP1 Registers (Continued)
HEX ADDRESS RANGE McASP0 01B4 C0C8 01B4 C0CC - 01B4 C0FC 01B4 C100 01B4 C104 01B4 C108 01B4 C10C 01B4 C110 01B4 C114 01B4 C118 01B4 C11C 01B4 C120 01B4 C124 01B4 C128 01B4 C12C 01B4 C130 01B4 C134 01B4 C138 01B4 C13C 01B4 C140 01B4 C144 01B4 C148 01B4 C14C 01B4 C150 01B4 C154 01B4 C158 01B4 C15C 01B4 C160 - 01B4 C17C 01B4 C180 01B4 C184 01B4 C188 01B4 C18C 01B4 C190 01B4 C194 01B4 C198 01B4 C19C 01B4 C1A0 - 01B4 C1FC 01B4 C200 01B4 C204 01B4 C208 01B4 C20C 01B4 C210 McASP1 01B5 00C8 01B5 00CC - 01B5 00FC 01B5 0100 01B5 0104 01B5 0108 01B5 010C 01B5 0110 01B5 0114 01B5 0118 01B5 011C 01B5 0120 01B5 0124 01B5 0128 01B5 012C 01B5 0130 01B5 0134 01B5 0138 01B5 013C 01B5 0140 01B5 0144 01B5 0148 01B5 014C 01B5 0150 01B5 0154 01B5 0158 01B5 015C 01B5 0160 - 01B5 017C 01B5 0180 01B5 0184 01B5 0188 01B5 018C 01B5 0190 01B5 0194 01B5 0198 01B5 019C 01B5 C1A0 - 01B5 01FC 01B5 0200 01B5 0204 01B5 0208 01B5 020C 01B50C210 ACRONYM XCLKCHK - DITCSRA0 DITCSRA1 DITCSRA2 DITCSRA3 DITCSRA4 DITCSRA5 DITCSRB0 DITCSRB1 DITCSRB2 DITCSRB3 DITCSRB4 DITCSRB5 DITUDRA0 DITUDRA1 DITUDRA2 DITUDRA3 DITUDRA4 DITUDRA5 DITUDRB0 DITUDRB1 DITUDRB2 DITUDRB3 DITUDRB4 DITUDRB5 - SRCTL0 SRCTL1 SRCTL2 SRCTL3 SRCTL4 SRCTL5 SRCTL6 SRCTL7 - XBUF0 XBUF1 XBUF2 XBUF3 XBUF4 REGISTER NAME Transmit clock check control register Reserved Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Left (even TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Right (odd TDM slot) channel status register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file Left (even TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Right (odd TDM slot) user data register file Reserved Serializer 0 control register Serializer 1 control register Serializer 2 control register Serializer 3 control register Serializer 4 control register Serializer 5 control register Serializer 6 control register Serializer 7 control register Reserved Transmit Buffer for Serializer 0 Transmit Buffer for Serializer 1 Transmit Buffer for Serializer 2 Transmit Buffer for Serializer 3 Transmit Buffer for Serializer 4 Right (odd TDM slot) channel status register file
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
peripheral register descriptions (continued)
Table 10. McASP0 and McASP1 Registers (Continued)
HEX ADDRESS RANGE McASP0 01B4 C214 01B4 C218 01B4 C21C 01B4 C220 - 01B4 C27C 01B4 C280 01B4 C284 01B4 C288 01B4 C28C 01B4 C290 01B4 C294 01B4 C298 01B4 C29C 01B4 C2A0 - 01B4 FFFF McASP1 01B5 0214 01B5 0218 01B5 021C 01B5 C220 - 01B5 027C 01B5 0280 01B5 0284 01B5 0288 01B5 028C 01B5 0290 01B5 0294 01B5 0298 01B5 029C 01B5 02A0 - 01B5 3FFF ACRONYM XBUF5 XBUF6 XBUF7 - RBUF0 RBUF1 RBUF2 RBUF3 RBUF4 RBUF5 RBUF6 RBUF7 - REGISTER NAME Transmit Buffer for Serializer 5 Transmit Buffer for Serializer 6 Transmit Buffer for Serializer 7 Reserved Receive Buffer for Serializer 0 Receive Buffer for Serializer 1 Receive Buffer for Serializer 2 Receive Buffer for Serializer 3 Receive Buffer for Serializer 4 Receive Buffer for Serializer 5 Receive Buffer for Serializer 6 Receive Buffer for Serializer 7 Reserved
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Table 11. I2C0 Registers
HEX ADDRESS RANGE 01B4 0000 01B4 0004 01B4 0008 01B4 000C 01B4 0010 01B4 0014 01B4 0018 01B4 001C 01B4 0020 01B4 0024 01B4 0028 01B4 002C 01B4 0030 01B4 0034 - 01B4 3FFF ACRONYM I2COAR0 I2CIER0 I2CSTR0 I2CCLKL0 I2CCLKH0 I2CCNT0 I2CDRR0 I2CSAR0 I2CDXR0 I2CMDR0 I2CISRC0 - I2CPSC0 - REGISTER NAME I2C0 own address register I2C0 interrupt enable register I2C0 interrupt status register I2C0 clock low-time divider register I2C0 clock high-time divider register I2C0 data count register I2C0 data receive register I2C0 slave address register I2C0 data transmit register I2C0 mode register I2C0 interrupt source register Reserved I2C0 prescaler register Reserved
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peripheral register descriptions (continued)
Table 12. I2C1 Registers
HEX ADDRESS RANGE 01B4 4000 01B4 4004 01B4 4008 01B4 400C 01B4 4010 01B4 4014 01B4 4018 01B4 401C 01B4 4020 01B4 4024 01B4 4028 01B4 402C 01B4 4030 01B4 4034 - 01B4 7FFF ACRONYM I2COAR1 I2CIER1 I2CSTR1 I2CCLKL1 I2CCLKH1 I2CCNT1 I2CDRR1 I2CSAR1 I2CDXR1 I2CMDR1 I2CISRC1 - I2CPSC1 - REGISTER NAME I2C1 own address register I2C1 interrupt enable register I2C1 interrupt status register I2C1 clock low-time divider register I2C1 clock high-time divider register I2C1 data count register I2C1 data receive register I2C1 slave address register I2C1 data transmit register I2C1 mode register I2C1 interrupt source register Reserved I2C1 prescaler register Reserved
Table 13. HPI Registers
HEX ADDRESS RANGE - - 0188 0000 0188 0001 - 018B FFFF ACRONYM HPID HPIA HPIC - REGISTER NAME HPI data register HPI address register HPI control register Reserved COMMENTS Host read/write access only Host read/write access only Both Host/CPU read/write access
Table 14. McBSP 0 Registers
HEX ADDRESS RANGE 018C 0000 0x3000 0000 - 0x33FF FFFF 018C 0004 0x3000 0000 - 0x33FF FFFF 018C 0008 018C 000C 018C 0010 018C 0014 018C 0018 018C 001C 018C 0020 018C 0024 018C 0028 - 018F FFFF ACRONYM DRR0 DRR0 DXR0 DXR0 SPCR0 RCR0 XCR0 SRGR0 MCR0 RCER0 XCER0 PCR0 - REGISTER NAME McBSP0 data receive register via Peripheral Bus McBSP0 data receive register via EDMA Bus McBSP0 data transmit register via Peripheral Bus McBSP0 data transmit register via EDMA Bus McBSP0 serial port control register McBSP0 receive control register McBSP0 transmit control register McBSP0 sample rate generator register McBSP0 multichannel control register McBSP0 receive channel enable register McBSP0 transmit channel enable register McBSP0 pin control register Reserved COMMENTS The CPU and DMA/EDMA controller can only read this register; they cannot write to it.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
peripheral register descriptions (continued)
Table 15. McBSP 1 Registers
HEX ADDRESS RANGE 0190 0000 0x3400 0000 - 0x37FF FFFF 0190 0004 0x3400 0000 - 0x37FF FFFF 0190 0008 0190 000C 0190 0010 0190 0014 0190 0018 0190 001C 0190 0020 ACRONYM DRR1 DRR1 DXR1 DXR1 SPCR1 RCR1 XCR1 SRGR1 MCR1 RCER1 XCER1 PCR1 - REGISTER NAME Data receive register via Peripheral Bus McBSP1 data receive register via EDMA Bus McBSP1 data transmit register via Peripheral Bus McBSP1 data transmit register via EDMA Bus McBSP1 serial port control register McBSP1 receive control register McBSP1 transmit control register McBSP1 sample rate generator register McBSP1 multichannel control register McBSP1 receive channel enable register McBSP1 transmit channel enable register McBSP1 pin control register Reserved COMMENTS The CPU and DMA/EDMA controller can only read this register; they cannot write to it.
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0190 0024 0190 0028 - 0193 FFFF
Table 16. Timer 0 Registers
HEX ADDRESS RANGE 0194 0000 ACRONYM CTL0 REGISTER NAME Timer 0 control register COMMENTS Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.
0194 0004 0194 0008 0194 000C - 0197 FFFF
PRD0 CNT0 -
Timer 0 period register Timer 0 counter register Reserved
Table 17. Timer 1 Registers
HEX ADDRESS RANGE 0198 0000 ACRONYM CTL1 REGISTER NAME Timer 1 control register COMMENTS Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin. Contains the number of timer input clock cycles to count. This number controls the TSTAT signal frequency. Contains the current value of the incrementing counter.
0198 0004 0198 0008 0198 000C - 019B FFFF
PRD1 CNT1 -
Timer 1 period register Timer 1 counter register Reserved
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peripheral register descriptions (continued)
Table 18. GPIO Registers
HEX ADDRESS RANGE 01B0 0000 01B0 0004 01B0 0008 01B0 000C 01B0 0010 01B0 0014 01B0 0018 01B0 001C 01B0 0020 01B0 0024 01B0 0028 - 01B0 3FFF ACRONYM GPEN GPDIR GPVAL - GPDH GPHM GPDL GPLM GPGC GPPOL - REGISTER NAME GPIO enable register GPIO direction register GPIO value register Reserved GPIO delta high register GPIO high mask register GPIO delta low register GPIO low mask register GPIO global control register GPIO interrupt polarity register Reserved
PWRD bits in CPU CSR register description
Table 19 identifies the PWRD field (bits 15-10) in the CPU CSR register. These bits control the device power-down modes. For more detailed information on the PWRD bit field of the CPU CSR register, see the TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table 19. PWRD field bits in the CPU CSR Register
HEX ADDRESS RANGE - ACRONYM CSR REGISTER NAME Control status register COMMENTS The PWRD field (bits 15-10 in the CPU CSR) controls the device power-down modes. Accessible by writing a value to the CSR register.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
interrupts and interrupt selector
The C67x DSP core supports 16 prioritized interrupts, which are listed in Table 20. The highest priority interrupt is INT_00 (dedicated to RESET) while the lowest priority is INT_15. The first four interrupts are non-maskable and fixed. The remaining interrupts (4-15) are maskable and default to the interrupt source listed in Table 20. However, their interrupt source may be reprogrammed to any one of the sources listed in Table 21 (Interrupt Selector). Table 21 lists the selector value corresponding to each of the alternate interrupt sources. The selector choice for interrupts 4-15 is made by programming the corresponding fields (listed in Table 20) in the MUXH (address 0x019C0000) and MUXL (address 0x019C0004) registers. Table 20. DSP Interrupts
DSP INTERRUPT NUMBER INT_00 INT_01 INT_02 INT_03 INT_04 INT_05 INT_06 INT_07 INT_08 INT_09 INT_10 INT_11 INT_12 INT_13 INT_14 INT_15 INTERRUPT SELECTOR CONTROL REGISTER - - - - MUXL[4:0] MUXL[9:5] MUXL[14:10] MUXL[20:16] MUXL[25:21] MUXL[30:26] MUXH[4:0] MUXH[9:5] MUXH[14:10] MUXH[20:16] MUXH[25:21] MUXH[30:26] DEFAULT SELECTOR VALUE (BINARY) - - - - 00100 00101 00110 00111 01000 01001 00011 01010 01011 00000 00001 00010 DEFAULT INTERRUPT EVENT RESET NMI Reserved Reserved EXTINT4 EXTINT5 EXTINT6 EXTINT7 EDMAINT EMUDTDMA SDINT EMURTDXRX EMURTDXTX DSPINT TINT0 TINT1
Table 21. Interrupt Selector
INTERRUPT SELECTOR VALUE (BINARY) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 INTERRUPT EVENT DSPINT TINT0 TINT1 SDINT EXTINT4 EXTINT5 EXTINT6 EXTINT7 EDMAINT EMUDTDMA EMURTDXRX EMURTDXTX XINT0 RINT0 XINT1 RINT1 GPINT0 Reserved Reserved Reserved Reserved Reserved I2CINT0 I2CINT1 Reserved Reserved Reserved Reserved AXINT0 ARINT0 AXINT1 ARINT1 MODULE
HPI Timer 0 Timer 1 EMIF GPIO GPIO GPIO GPIO EDMA Emulation Emulation Emulation McBSP0 McBSP0 McBSP1 McBSP1 GPIO - - - - - I2C0 I2C1 - - - - McASP0 McASP0 McASP1 McASP1
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EDMA module and EDMA selector
The C67x EDMA supports up to 16 EDMA channels. Four of the sixteen channels (channels 8-11) are reserved for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices. The EDMA selector registers that control the EDMA channels servicing peripheral devices are located at addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), and 0x01A0FF0C (ESEL3). These EDMA selector registers control the mapping of the EDMA events to the EDMA channels. Each EDMA event has an assigned EDMA selector code (see Table 23). By loading each EVTSELx register field with an EDMA selector code, users can map any desired EDMA event to any specified EDMA channel. Table 22 lists the default EDMA selector value for each EDMA channel. See Table 24 and Table 25 for the EDMA Event Selector registers and their assoicated bit descriptions.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
EDMA module and EDMA selector (continued)
Table 22. EDMA Channels
EDMA CHANNEL 0 1 2 3 4 5 6 7 8 9 10 11 EDMA SELECTOR CONTROL REGISTER ESEL0[5:0] ESEL0[13:8] ESEL0[21:16] ESEL0[29:24] ESEL1[5:0] ESEL1[13:8] ESEL1[21:16] ESEL1[29:24] n/a n/a n/a n/a ESEL3[5:0] ESEL3[13:8] ESEL3[21:16] ESEL3[29:24] DEFAULT SELECTOR VALUE (BINARY) 000000 000001 000010 000011 000100 000101 000110 000111 n/a n/a n/a n/a 001000 001001 001010 001011 DEFAULT EDMA EVENT DSPINT TINT0 TINT1 SDINT EXTINT4 EXTINT5 EXTINT6 EXTINT7 TCC8 (Chaining) TCC9 (Chaining) TCC10 (Chaining) TCC11 (Chaining) XEVT0 REVT0 XEVT1 REVT1
Table 23. EDMA Selector
EDMA SELECTOR CODE (BINARY) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000-011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000-111111 EDMA EVENT DSPINT TINT0 TINT1 SDINT EXTINT4 EXTINT5 EXTINT6 EXTINT7 GPINT0 GPINT1 GPINT2 GPINT3 XEVT0 REVT0 XEVT1 REVT1 Reserved AXEVTE0 AXEVTO0 AXEVT0 AREVTE0 AREVTO0 AREVT0 AXEVTE1 AXEVTO1 AXEVT1 AREVTE1 AREVTO1 AREVT1 I2CREVT0 I2CXEVT0 I2CREVT1 I2CXEVT1 GPINT8 GPINT9 GPINT10 GPINT11 GPINT12 GPINT13 GPINT14 GPINT15 Reserved McASP0 McASP0 McASP0 McASP0 McASP0 McASP0 McASP1 McASP1 McASP1 McASP1 McASP1 McASP1 I2C0 I2C0 I2C1 I2C1 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO MODULE
HPI TIMER0 TIMER1 EMIF GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO McBSP0 McBSP0 McBSP1 McBSP1
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12 13 14 15
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EDMA module and EDMA selector (continued)
Table 24. EDMA Event Selector Registers (ESEL0, ESEL1, and ESEL3) ESEL0 Register (0x01A0 FF00)
31 30 29 28 27 24 23 22 21 20 19 16
Reserved R-0
15 14 13 12
EVTSEL3 R/W-00 0011b
11 8 7
Reserved R-0
6 5 4
EVTSEL2 R/W-00 0010b
3
0 EVTSEL0
Reserved R-0
EVTSEL1 R/W-00 0001b
Reserved R-0
R/W-00 0000b
Legend: R = Read only, R/W = Read/Write; -n = value after reset
ESEL1 Register (0x01A0 FF04)
31 30 29 28 27 24 23 22 21 20 19 16
R-0
15 14 13 12
R/W-00 0111b
11 8 7
R-0 65 Reserved R-0
4
R/W-00 0110b
3
0 EVTSEL4
Reserved R-0
EVTSEL5 R/W-00 0101b
R/W-00 0100b
Legend: R = Read only, R/W = Read/Write; -n = value after reset
ESEL3 Register (0x01A0 FF0C)
31 30 29 28 27 24 23 22 21 20 19 16
Reserved R-0
15 14 13 12
EVTSEL15 R/W-00 1011b
11 8 7
Reserved R-0
6 5 4
EVTSEL14 R/W-00 1010b
3 0
Reserved R-0
EVTSEL13 R/W-00 1001b
Reserved R-0
EVTSEL12 R/W-00 1000b
Legend: R = Read only, R/W = Read/Write; -n = value after reset
Table 25. EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description
BIT # 31:30 23:22 15:14 7:6 NAME DESCRIPTION
Reserved
Reserved. Read-only, writes have no effect.
EDMA event selection bits for channel x. Allows mapping of the EDMA events to the EDMA channels. 29:24 21:16 13:8 5:0 The EVTSEL0 through EVTSEL15 bits correspond to the channels 0 to 15, respectively. These EVTSELx fileds are user-selectable. By configuring the EVTSELx fields to the EDMA selector value of the desired EDMA sync event number (see Table 23), users can map any EDMA event to the EDMA channel. For example, if EVTSEL15 is programmed to 00 0001b (the EDMA selector code for TINT0), then channel 15 is triggered by Timer0 TINT0 events.
EVTSELx
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Reserved
EVTSEL7
Reserved
EVTSEL6
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
signal groups description
CLKIN CLKOUT2/GP[2] CLKOUT3 CLKMODE0 PLLV PLLG OSCIN OSCOUT Clock/PLL Oscillator
PRODUCT PREVIEW
TMS TDO TDI TCK TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5
Reset and Interrupts
RESET NMI GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1
IEEE Standard 1149.1 (JTAG) Emulation
Control/Status
HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8] HD7/GP[3] HD6/AHCLKR1 HD5/AHCLKX1 HD4/GP[0] HD3/AMUTE1 HD2/AFSX1 HD1/AXR1[7] HD0/AXR1[4]
HPI (Host-Port Interface) HAS/ACLKX1 HR/W/AXR1[0] HCS/AXR1[2] HDS1/AXR1[6] HDS2/AXR1[5] HRDY/ACLKR1 HINT/GP[1]
Control
Data
Register Select
HCNTL0/AXR1[3] HCNTL1/AXR1[1]
Half-Word Select
HHWIL/AFSR1
These external pins are applicable to the GFN package only. NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.
Figure 3. CPU (DSP Core) and Peripheral Signals
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
signal groups description (continued)
HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8]
GPIO
GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1 HD7/GP[3] CLKOUT2/GP[2] HINT/GP[1] HD4/GP[0]
General-Purpose Input/Output (GPIO) Port
TOUT1/AXR0[4] TINP1/AHCLKX0
Timer 1
Timer 0
TOUT0/AXR0[2] TINP0/AXR0[3]
Timers
CLKS1/SCL1 DR1/SDA1
I2C1 I2Cs
I2C0
SCL0 SDA0
NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.
Figure 4. Peripheral Signals
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
signal groups description (continued)
ED[31:16] ED[15:0]
16 16 Data Memory Control
ECLKIN ECLKOUT ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE ARDY
CE3 CE2 CE1 CE0 EA[21:2] BE3 BE2 20
Memory Map Space Select Bus Arbitration HOLD HOLDA BUSREQ
Address
PRODUCT PREVIEW
BE1 BE0
Byte Enables EMIF (External Memory Interface)
McBSP1
McBSP0
CLKX1/AMUTE0 FSX1 DX1/AXR0[5]
Transmit
Transmit
CLKX0/ACLKX0 FSX0/AFSX0 DX0/AXR0[1]
CLKR1/AXR0[6] FSR1/AXR0[7] DR1/SDA1
Receive
Receive
CLKR0/ACLKR0 FSR0/AFSR0 DR0/AXR0[0]
CLKS1/SCL1
Clock
Clock
CLKS0/AHCLKR0
McBSPs (Multichannel Buffered Serial Ports)
These external pins are applicable to the GFN package only. NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.
Figure 4. Peripheral Signals (Continued)
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signal groups description (continued)
(Transmit/Receive Data Pins) FSR1/AXR0[7] CLKR1/AXR0[6] DX1/AXR0[5] TOUT1/AXR0[4] TINP0/AXR0[3] TOUT0/AXR0[2] DX0/AXR0[1] DR0/AXR0[0]
8-Serial Ports Flexible Partitioning Tx, Rx, OFF
(Receive Bit Clock) CLKR0/ACLKR0 TINP1/AHCLKX0 (Receive Master Clock) Transmit Clock Check Circuit Receive Clock Generator Transmit Clock Generator
(Transmit Bit Clock) CLKX0/ACLKX0 CLKS0/AHCLKR0 (Transmit Master Clock)
Receive Clock Check Circuit
FSR0/AFSR0 (Receive Frame Sync or Left/Right Clock)
Receive Frame Sync
Transmit Frame Sync
FSX0/AFSX0 (Transmit Frame Sync or Left/Right Clock) CLKX1/AMUTE0 GP[5](EXT_INT5)/AMUTEIN0
Error Detect (see Note A)
Auto Mute Logic
McASP0 (Multichannel Audio Serial Port 0)
NOTES: A. The McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.
Figure 4. Peripheral Signals (Continued)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
signal groups description (continued)
(Transmit/Receive Data Pins) HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1] HR/W/AXR1[0]
8-Serial Ports Flexible Partitioning Tx, Rx, OFF
(Receive Bit Clock) HRDY/ACLKR1 HD6/AHCLKR1 (Receive Master Clock) Receive Clock Generator Transmit Clock Generator
(Transmit Bit Clock) HAS/ACLKX1 HD5/AHCLKX1 (Transmit Master Clock) Transmit Clock Check Circuit
PRODUCT PREVIEW
Receive Clock Check Circuit
HHWIL/AFSR1 (Receive Frame Sync or Left/Right Clock)
Receive Frame Sync
Transmit Frame Sync
HD2/AFSX1 (Transmit Frame Sync or Left/Right Clock) HD3/AMUTE1 GP[4](EXT_INT4)/AMUTEIN1
Error Detect (see Note A)
Auto Mute Logic
McASP1 (Multichannel Audio Serial Port 1)
NOTES: A. The McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.
Figure 4. Peripheral Signals (Continued)
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DEVICE CONFIGURATIONS
On the C6713 device, bootmode and certain device configurations/peripheral selections are determined at device reset, while other device configurations/peripheral selections are software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200] after device reset.
device configurations at device reset
Table 26 describes the C6713 device configuration pins, which are set up via external pullup/pulldown resistors through the HPI data pins (HD[4:3], HD8, and HD12) and CLKMODE0 pin. For more details on these device configuration pins, see the Terminal Functions table and the Debugging Considerations section. Table 26. Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0)
CONFIGURATION PIN HD8 PYP GFN FUNCTIONAL DESCRIPTION Device Endian mode (LEND) 0 - System operates in Big Endian mode 1 - System operates in Little Endian mode (default) Bootmode Configuration Pins (BOOTMODE) 00 - CE1 width 32-bit, HPI boot 01 - CE1 width 8-bit, Asynchronous external ROM boot with default timings (default mode) 10 - CE1 width 16-bit, Asynchronous external ROM boot 11 - CE1 width 32-bit, Asynchronous external ROM boot Pulldown. For proper device operation, this pin must be externally pulled down with a 1-k resistor. Clock generator input clock source select 0 - Oscillator pads (OSCIN, OSCOUT directly from the crystal oscillator) 1 - CLKIN square wave [default]
B17
HD[4:3] (BOOTMODE)
A15, C19, C20
HD12
C15
CLKMODE0
C4
This pin must be pulled to the correct level even after reset. Other HD pins (HD [15, 13, 11:9, 7:5, 2:0] have pullups/pulldowns (IPUs/IPDs). For proper device operation, do not oppose these pins with external IPUs/IPDs at reset.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
DEVICE CONFIGURATIONS (CONTINUED) peripheral selection at device reset
Some C6713 peripherals share the same pins but are mutually exclusive (i.e., HPI, general-purpose input/output 0 pins GP[15:8, 3, 1, 0], McASP0, and I2C0).
D HPI versus McASP1, I2C0, and GP peripherals
The HPI_EN (HD14 pin) is latched at reset. This pin selects whether the HPI peripheral or McASP1, I2C0 peripherals, and GP[15:8, 3, 1, 0] pins are functionally enabled (see Table 27). Table 27. HPI_EN (HD14 Pin) Peripheral Selection (HPI or McASP1, I2C0, and Select GP Pins)
PERIPHERAL SELECTION HPI_EN (HD14 Pin) PERIPHERALS SELECTED HPI McASP1, I2C0, and GP [15:8,3,1,0] DESCRIPTION
PRODUCT PREVIEW
0
HPI_EN = 0 HPI is disabled; McASP1 and I2C0 peripherals and GP [15:8, 3, 1,0] pins are enabled. All multiplexed HPI/McASP1 and HPI/GP pins function as McASP1 and GP pins, respectively. To use the GP pins, the appropriate bits in the GPEN and GPDIR registers need to be configured. The IPUs on the I2C0 pins are disabled, allowing for I2C0 use. When the I2C0 peripheral is not used, to avoid floating inputs, these I2C0 pins must be externally pulled up with 1-k resistor. HPI_EN = 1 HPI is enabled; McASP1 and I2C0 peripherals and GP [15:8, 3, 1,0] pins are disabled [default]. All multiplexed HPI/McASP1 and HPI/GP pins function as HPI pins. In addition, since the I2C0 peripheral is disabled, the IPUs on the I2C0 pins are enabled to avoid floating inputs.
1
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DEVICE CONFIGURATIONS (CONTINUED) peripheral selection/device configurations via the DEVCFG control register
The device configuration register (DEVCFG) allows the user to control the peripheral selection of the McBSP0, McBSP1, McASP0, and I2C1 peripherals. The DEVCFG register also offers the user control of the EMIF input clock source and the timer output functions of the TOUT1/AXR0[4] and TOUT0/AXR0[2] multiplexed pins. For more detailed information on the DEVCFG register control bits, see Table 28 and Table 29. Table 28. Device Configuration Register (DEVCFG) [Address location: 0x019C0200]
31 Reserved RW-0 15 Reserved RW-0 Legend: R/W = Read/Write; -n = value after reset Do not write non-zero values to these bit locations. 5 4 EKSRC R/W-0 3 TOUT1SEL R/W-0 2 TOUT0SEL R/W-0 1 McASP0EN R/W-0 0 I2C1EN R/W-0 16
Table 29. Device Configuration (DEVCFG) Register Selection Bit Descriptions
BIT # 31:5 NAME Reserved DESCRIPTION Reserved. Do not write non-zero values to these bit locations. EMIF input clock source bit. Determines which clock signal is used as the EMIF input clock. 0 = SYSCLK3 (from the clock generator) is the EMIF input clock source (default) 1 = ECLKIN external pin is the EMIF input clock source Timer 1 output (TOUT1) pin function select bit. Selects the pin function of the TOUT1/AXR0[4] external pin independent of the rest of the peripheral selection bits in the DEVCFG register. 0 = The pin functions as a Timer 1 output (TOUT1) pin (default) 1 = The pin functions as the McASP0 AXR0[4] pin. Timer 0 output (TOUT0) pin function select bit. Selects the pin function of the TOUT0/AXR0[2] external pin independent of the rest of the peripheral selection bits in the DEVCFG register. 0 = The pin functions as a Timer 0 output (TOUT0) pin (default) 1 = The pin functions as the McASP0 AXR0[2] pin. Multichannel Audio Serial Port 0 (McASP0) enable bit. Selects whether McASP0 or the McBSP0 peripheral is enabled. 0 = McASP0 is disabled (functional for DIT mode only), McBSP0 is enabled (default). 1 = McASP0 is enabled, McBSP0 is disabled. Inter-integrated circuit 1 (I2C1) enable bit. Selects whether I2C1 or the McBSP1 peripheral is enabled. 0 = I2C1 is disabled, McBSP1 is enabled (default) The internal IPU/IPDs on the CLKS1/SCL1 and DR1/SDA1 pins are enabled for McBSP1's use. 1 = I2C1 is enabled, McBSP1 is disabled The internal IPU/IPDs on the CLKS1/SCL1 and DR1/SDA1 pins are disabled for I2C1's use
4
EKSRC
3
TOUT1SEL
2
TOUT0SEL
1
MCASP0EN
0
I2C1EN
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
DEVICE CONFIGURATIONS (CONTINUED) multiplexed pins
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Most of these pins are configured by software via the device configuration register (DEVCFG), and the others (specifically, the HPI pins) are configured by an external pullup/pulldown resistor on the HD14 pin (HPI_EN) at reset. The muxed pins that are configured by software are intended to be programmed once during software initialization. The muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 30 summarizes the peripheral pins affected by the HPI_EN (HD14 pin) and DEVCFG register. Table 31 identifies the multiplexed pins on the C6713 device; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure the specific multiplexed functions.
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DEVICE CONFIGURATIONS (CONTINUED)
Table 30. Peripheral Pin Selection Matrix
SELECTION BITS B I T N A M E B I T V A L U E PERIPHERAL PINS AVAILABILITY T I M E R 0 T I M E R 1 G P I O P I N S GP[0:1], GP[3], GP[8:15] All None Plus: GP2 ctrl'd by GP2EN NO GP[0:1], GP[3], GP[8:15]
M c A S P 0
M c A S P 1
I 2 C 0
I 2 C 1
M c B S P 0
M c B S P 1
H P I
E M I F
0 HPI_EN (boot config pin)
1
None
None
All
0
None ACLKK0 ACLKR0 AFSX0 AFSR0 AHCLKR0 AXR0[0] AXR0[1] NO AMUTE0 AXR0[5] AXR0[6] AXR0[7] AMUTE0 AXR0[5] AXR0[6] AXR0[7] NO AXR0[2] AXR0[2] NO AXR0[4] AXR0[4]
All
McASP0EN (DEVCFG bit)
1
None
0 IIC1EN (DEVCFG bit) 1
None
All
All
None
0 TOUT0SEL (DEVCFG bit) 1 0 TOUT1SEL (DEVCFG bit) 1
TOUT0 NO TOUT0 TOUT1 NO TOUT1
Gray blocks indicate that the peripheral is not affected by the selection bit. The McASP0 pins AXR0[3] and AHCLKX0 are shared with the timer input pins TINP0 and TINP1, respectively. See Table 31 for more detailed information.
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AHCLKX1 AHCLKR1 ACLKX1 ACLKR1 AFSX1 AFSR1 AMUTE1 AXR1[0] to AXR1[7]
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
DEVICE CONFIGURATIONS (CONTINUED)
Table 31. C6713 Device Multiplexed/Shared Pins
MULTIPLEXED PINS NAME PYP GFN DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION When the CLKOUT2 pin is enabled , the CLK2EN bit in the EMIF global control register (GBLCTL) controls the CLKOUT2 pin. CLK2EN = 0: CLKOUT2 held high CLK2EN = 1: CLKOUT2 enabled to clock To use these as GPIO pins, the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an input GPxDIR = 1: GPx pin is an output To use AMUTEIN0/1 pin function, the GP[5]/GP[4] pins must be configured as an input, and set to 1 the INSTAT bit in the associated McASP AMUTE register.
CLKOUT2/GP[2]
Y12
CLKOUT2
GP2EN = 0 (GPEN reigster bit) GP[2] function disabled, CLKOUT2 enabled
PRODUCT PREVIEW
GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1
C1 C2
GP[5](EXT_INT5) GP[4](EXT_INT4)
No Function GP5EN = 0 (disabled) GP4EN = 0 (disabled) GPxDIR = 0 (input)
CLKS0/AHCLKR0 DR0/AXR0[0] DX0/AXR0[1] FSR0/AFSR0 FSX0/AFSX0 CLKR0/ACLKR0 CLKX0/ACLKX0 CLKS1/SCL1 DR1/SDA1 DX1/AXR0[5] FSR1/AXR0[7] CLKR1/AXR0[6] CLKX1/AMUTE0
K3 J1 H2 J3 H1 H3 G3 E1 McBSP1 pin function M2 L2 M3 M1 L3 McBSP1 pin function I2C1EN = 0 (DEVCFG register bit) I2C1 disabled, McBSP0 pins enabled I2C1EN = 0 (DEVCFG register bit) I2C1 disabled disabled, McBSP1 pins enabled To enable the I2C1 peripheral, the I2C1EN bit in the DEVCFG register must be set to 1, disabling the McBSP1 peripheral pins. To enable the McASP0 peripheral pins the I2C1EN bit in the DEVCFG register must be set to 1. McBSP0 pin function in MCASP0EN = 0 (DEVCFG register bit) i bi ) McASP0 pins disabled disabled, McBSP0 pins enabled ins To enable the McASP0 peripheral, the McASP0EN bit in h M ASP0EN bi i the DEVCFG register must be set to 1 (disabling the McBSP0 peripheral pins). eri heral ins).
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DEVICE CONFIGURATIONS (CONTINUED)
Table 31. C6713 Device Multiplexed/Shared Pins
MULTIPLEXED PINS NAME HINT/GP[1] HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8] HD7/GP[3] HD4/GP[0] HD1/AXR1[7] HD0/AXR1[4] HCNTL1/AXR1[1] HCNTL0/AXR1[3] HR/W/AXR1[0] HDS1/AXR1[6] HDS2/AXR1[5] HCS/AXR1[2] HD6/AHCLKR1 HD5/AHCLKX1 HD3/AMUTE1 HD2/AFSX1 HHWIL/AFSR1 HRDY/ACLKR1 HAS/ACLKX1 PYP GFN J20 B14 C14 A15 C15 A16 B16 C16 B17 A18 C19 D20 E20 G19 G18 G20 E9 F18 F20 H19 B18 C20 D18 H20 H19 E18 AXR3 bit in the McASP0 PDIR register = 0 (input) By default, this pin functions as TINP0 and AXR0[3] input. Setting the AXR3 bit in the McASP0 PDIR register to a 1 enables AXR0[3] as an output and disables the TINP0 pin function. By default, this pin functions as TINP1 and AHCLKX0 input. Setting the AHCLKX bit in the McASP0 PDIR register to a 1 enables AHCLKX0 as an output and disables the TINP1 pin function. HPI pin function HPI_EN (HD14 pin) = 1 (HPI enabled) McASP1, I2C0, and , , eleven GP pins are l i disabled disabled. To enable the McASP1 and I2C0 peripherals and the eleven GP pins, eri herals ins, an external pulldown resistor (1 k) must be provided on the HD14 pin setting HPI_EN = 0 at reset. HPI EN DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION
TINP0/AXR0[3]
G2
Both TINP0 and AXR0[3] input function
TINP1/AHCLKX0
F2
Both TINP1 and AHCLKX0 input function
AHCLKX bit in the McASP0 PDIR register = 0 (input)
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To use these as GPIO pins, the GPxEN bits in the GPIO Enable Register and the GPxDIR bits in the GPIO Direction Register must be properly configured. GPxEN = 1: GPx pin enabled GPxDIR = 0: GPx pin is an in ut input in GPxDIR = 1: GPx pin is an output
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
DEVICE CONFIGURATIONS (CONTINUED)
Table 31. C6713 Device Multiplexed/Shared Pins
MULTIPLEXED PINS NAME PYP GFN DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION To enable the McASP0 AXR0[2] pin, the following must be properly configured: TOUT0SEL = 0 (DEVCFG register bit) TOUT0 pin enabled and McASP0 AXR0[2] disabled TOUT0SEL = 1 (TOUT0 disabled, AXR0[2] enabled. If the AXR2 bit in the McASP0 PDIR register = 0, then AXR0[2] is an input pin. If the AXR2 bit in the McASP0 PDIR register = 1, then AXR0[2] is an output pin. To enable the McASP0 AXR0[4] pin, the following must be properly configured: TOUT1SEL = 0 (DEVCFG register bit) TOUT1 pin enabled and McASP0 AXR0[4] disabled TOUT1SEL = 1 (TOUT1 disabled, AXR0[4] enabled. If the AXR4 bit in the McASP0 PDIR register = 0, then AXR0[4] is an input pin. If the AXR4 bit in the McASP0 PDIR register = 1, then AXR0[4] is an output pin.
TOUT0/AXR0[2]
G1
Timer 0 output function
PRODUCT PREVIEW
TOUT1/AXR0[4]
F1
Timer 1 output function
configuration examples
Figure 5 through Figure 10 illustrate examples of peripheral selections that are configurable on this device.
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DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
ED [31:16], ED[15:0] EA[21:2] CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY 32 20 Clock, System, EMU, and Reset CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, NMI
EMIF
GP[15:8, 3:1] GPIO and EXT_INT GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
HPI
I2C0
SCL0, SDA0
SCL1, SDA1
I2C1
McASP1 8
AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0] 8 AXR0[7:0] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0
McBSP1
McASP0
TIMER0 McBSP0 TIMER1
Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000F McASP0EN = 1 I2C1EN = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (GPEN Register)
Figure 5. Configuration Example A (2 I2C + 2 McASP)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF Clock, System, EMU, and Reset CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, NMI
CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY
GP[15:8, 3:1] GPIO and EXT_INT GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
PRODUCT PREVIEW
HPI
I2C0
SCL0, SDA0
I2C1
McASP1 8
AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0]
5 AXR0[4:0] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0
DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1
McBSP1
McASP0
TIMER0 McBSP0 TIMER1
Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000E McASP0EN = 1 I2C1EN = 0 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (GPEN Register)
Figure 6. Configuration Example B (1 I2C + 1 McBSP + 2 McASP)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
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DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF Clock, System, EMU, and Reset CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, NMI
CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY
GP[15:8, 3:1] GPIO and EXT_INT GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
HPI
I2C0
SCL0, SDA0
SCL1, SDA1
I2C1
McASP1 8
AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0] 6
McBSP1
McASP0 (DIT Mode)
AXR0[7:2] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] AMUTE0, TINP1/AHCLKX0
TIMER0 DR0, CLKS0, CLKR0, CLKX0, FSR0, DX0, FSX0 McBSP0 TIMER1
Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000D McASP0EN = 0 I2C1EN = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (GPEN Register)
Figure 7. Configuration Example C [2 I2C + 1 McBSP + 1 McASP + 1 McASP (DIT)]
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF Clock, System, EMU, and Reset CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, NMI
CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY
GP[15:8, 3:1] GPIO and EXT_INT GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
PRODUCT PREVIEW
HPI
I2C0
SCL0, SDA0
I2C1
McASP1 8
AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0]
3 McASP0 (DIT Mode) AXR0[4:2] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] TINP1/AHCLKX0
DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1
McBSP1
TIMER0 DR0, CLKS0, CLKR0, CLKX0, FSR0, DX0, FSX0 McBSP0 TIMER1
Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000C McASP0EN = 0 I2C1EN = 0 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (GPEN Register)
Figure 8. Configuration Example D [1 I2C + 2 McBSP + 1 McASP + 1 McASP (DIT)]
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DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
ED [31:16], ED[15:0] EA[21:2] CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY 32 20 EMIF Clock, System, EMU, and Reset CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, NMI CLKOUT2
GPIO and EXT_INT
GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
16 HD[15:0] HPI HINT, HHWIL, HRDY, HR/W, HCNTRL1, HCNTRL0, HCS, HDS2, HDS1, HAS SCL1, SDA1 I2C1 McASP1 I2C0
8 AXR0[7:0], TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0
McBSP1
McASP0
TIMER0 McBSP0 TIMER1
Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000F McASP0EN = 1 I2C1EN = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 1 GP2EN BIT = 0 (GPEN Register)
Figure 9. Configuration Example E (1 I2C + HPI + 1 McASP)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
ED [31:16], ED[15:0] EA[21:2] CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY 32 20 EMIF Clock, System, EMU, and Reset CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, NMI CLKOUT2
GPIO and EXT_INT
GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
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PRODUCT PREVIEW
HD[15:0] HPI HINT, HHWIL, HRDY, HR/W, HCNTRL1, HCNTRL0, HCS, HDS2, HDS1, HAS I2C1 McASP1 I2C0
5 AXR0[4:0] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0
DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1
McBSP1
McASP0
TIMER0 McBSP0 TIMER1
Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000E McASP0EN = 1 I2C1EN = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 1 GP2EN BIT = 0 (GPEN Register)
Figure 10. Configuration Example F (1 McBSP + HPI + 1 McASP)
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DEVICE CONFIGURATIONS (CONTINUED) debugging considerations
It is recommended that external connections be provided to peripheral selection/device configuration pins, including HD[14:12, 8, 4, 3], and CLKMODE0. Although internal pullup resistors exist on these pins, providing external connectivity adds convenience to the user in debugging and flexibility in switching operating modes. Internal pullup/pulldown resistors also exist on the non-configuration pins on the HPI data bus (HD[15, 13, 11:9, 7:5, 2:0]). For proper device operation, do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown resistors. If an external controller provides signals to these non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven at all. For the internal pullup/pulldown resistors for all device pins, see the terminal functions table.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
TERMINAL FUNCTIONS
The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device Configurations section of this data sheet.
PRODUCT PREVIEW
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
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Terminal Functions
SIGNAL NAME PIN NO. PYP GFN TYPE IPD/ IPU CLOCK/PLL CONFIGURATION CLKIN CLKOUT2/GP[2] CLKOUT3 CLKMODE0 PLLV PLLG OSCIN OSCOUT TMS TDO TDI TCK TRST EMU5 EMU4 EMU3 EMU2 EMU1 EMU0 RESET NMI GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/ AMUTEIN0 GP[4](EXT_INT4)/ AMUTEIN1 -- -- -- -- A3 Y12 D10 C4 A4 C6 D12 C12 B7 A8 A7 A6 B6 B12 C11 B10 D3 B9 D9 A13 C13 E3 D2 C1 I/O/Z IPU I O/Z I I A A I O I O/Z I I I I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I I -- -- IPU IPU IPU IPU IPD IPU IPU IPU IPU IPU IPU IPU IPD IPD IPD IPD IPU Clock Input Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the clock generator) or this pin can be programmed as GP[2] pin (I/O/Z) Programmable clock output (OSC Divider internal signal from clock generator) Clock generator input clock source select 0 - Oscillator pads (OSCIN, OSCOUT directly from the crystal oscillator) 1 - CLKIN square wave [default] Analog power (1.2 V) for PLL Analog ground for PLL Crystal oscillator Input (XI) Crystal oscillator output (XO) JTAG EMULATION JTAG test-port mode select JTAG test-port data in JTAG test-port clock JTAG test-port reset Emulation pin 5. Reserved for future use, leave unconnected. Emulation pin 4. Reserved for future use, leave unconnected. Emulation pin 3. Reserved for future use, leave unconnected. Emulation pin 2. Reserved for future use, leave unconnected. Emulation pin 1 Emulation pin 0 Device reset Nonmaskable interrupt * Edge-driven (rising edge) General-purpose input/output pins (I/O/Z) which also function as external interrupts [default] * Edge-driven * Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]) GP[4] and GP[5] pins also f d i l function as AMUTEIN1 M ASP1 mute i ti McASP1 t input and td AMUTEIN0 McASP0 mute input, respectively, if enabled by the INSTAT bit in the McASP AMUTE register. JTAG test-port data out DESCRIPTION
RESETS AND INTERRUPTS
C2
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) A = Analog signal (PLL Filter) The EMU0 and EMU1 pins are internally pulled up with 30-k resistors; therefore, for emulation and normal operation, no external pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-k resistor.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
Terminal Functions (Continued)
SIGNAL NAME PIN NO. PYP GFN TYPE IPD/ IPU HOST-PORT INTERFACE (HPI) HINT/GP[1] HCNTL1/AXR1[1] HCNTL0/AXR1[3] J20 G19 G18 O/Z I I IPU IPU IPU Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as a GP[1] pin (I/O/Z). Host control - selects between control, address, or data registers (I) [default] or McASP1 data pin 1 (I/O/Z). Host control - selects between control, address, or data registers (I) [default] or McASP1 data pin 3 (I/O/Z). Host half-word select - first or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK) (I/O/Z). Host read or write select (I) [default] or McASP1 data pin 0 (I/O/Z). Host-port data pins (I/O/Z) [default] or general-purpose input/output pins (I/O/Z) * Used for transfer of data, address, and control data address * Also controls initialization of DSP modes at reset via pullup/pulldown resistors - Device Endian mode (HD8) 0 - Big Endian 1 - Little Endian - Boot mode (HD[4:3]) 00 - CE1 width 32-bit, HPI boot 01 - CE1 width 8-bit, Asynchronous external ROM boot with default timings (default mode) 10 - CE1 width 16-bit, Asynchronous external ROM boot 11 - CE1 width 32-bit, Asynchronous external ROM boot - HPI_EN (HD14) - HPI disabled, McASP1 and I2C0 enabled 0 1 - HPI enabled, McASP1 and I2C0 disabled (default) For proper device operation, the HD12 pin must be externally pulled down with a 1-k resistor. IPU , , ] ) Other HD pins ( (HD [ , 13, 11:9, 7:5, 2:0] have pullups/pulldowns ( [15, , (IPUs/IPDs). For proper device operation, do not oppose these pins with external IPUs/IPDs at reset. For more details, see the Device Configurations section of this data sheet. Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master clock (I/O/Z). Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master clock (I/O/Z). Host-port data pin 4 (I/O/Z) [ default] or this pin can be programmed as a GP 0 pin (I/O/Z). Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (I/O/Z). Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/right clock (LRCLK) (I/O/Z). Host-port data pin 1 (I/O/Z) [ default] or McASP1 data pin 7 (I/O/Z). DESCRIPTION
HHWIL/AFSR1 HR/W/AXR1[0] HD15/GP[15]
H20 G20 B14
I I
IPU IPU IPU
HD14/GP[14]
C14
IPU
PRODUCT PREVIEW
HD13/GP[13]
A15
IPU
HD12/GP[12]
C15
IPU
HD11/GP[11]
A16
IPU
HD10/GP[10]
B16
IPU
HD9/GP[9]
C16 I/O/Z
IPU
HD8/GP[8]
B17
HD7/GP[3] HD6/AHCLKR1 HD5/AHCLKX1 HD4/GP[0] HD3/AMUTE1 HD2/AFSX1 HD1/AXR1[7]
A18 C17 B18 C19 C20 D18 D20
IPU IPU IPU IPD IPU IPU IPU
HD0/AXR1[4] E20 IPU Host-port data pin 0 (I/O/Z) [ default] or McASP1 data pin 4 (I/O/Z). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.)
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Terminal Functions (Continued)
SIGNAL NAME HAS/ACLKX1 HCS/AXR1[2] HDS1/AXR1[6] HDS2/AXR1[5] HRDY/ACLKR1 CE3 CE2 CE1 CE0 BE3 BE2 BE1 BE0 HOLDA HOLD BUSREQ ECLKIN -- -- PIN NO. PYP GFN E18 F20 E19 F18 H19 V6 W6 W18 V17 V5 Y4 U19 V20 J18 J17 J19 Y11 TYPE IPD/ IPU DESCRIPTION
HOST-PORT INTERFACE (HPI) (CONTINUED) I I I I O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z O/Z I O/Z I IPU IPU IPU IPU IPD IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPD Byte-enable control * Decoded from the two lowest bits of the internal address y y y * Byte-write enables for most types of memory * C b di tl connected t SDRAM read and write mask signal (SDQM) Can be directly t d to d d it ki l Memory space enables * Enabled by bits 28 through 31 of the word address * Only one asserted during any external data access Host address strobe (I) [default] or McASP1 transmit bit clock (I/O/Z). Host chip select (I) [default] or McASP1 data pin 2 (I/O/Z). Host data strobe 1 (I) [default] or McASP1 data pin 6 (I/O/Z). Host data strobe 2 (I) [default] or McASP1 data pin 5 (I/O/Z) . Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z).
EMIF - COMMON SIGNALS TO ALL TYPES OF MEMORY
EMIF - BUS ARBITRATION Hold-request-acknowledge to the host Hold request from the host Bus request output External EMIF input clock source EMIF output clock depends on the EKSRC bit (DEVCFG.[16]). * EKSRC = 0 EMIF output clock source is the internal SYSCLK3 signal from the clock generator (default). * EKSRC = 1 ECLKOUT is based on the the external EMIF input clock source pin (ECLKIN). Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable Asynchronous memory ready input EMIF - ADDRESS EA21 EA20 EA19 EA18 EA17 U18 Y18 W17 Y16 V16 O/Z IPU External address (word address)
EMIF - ASYNCHRONOUS/SYNCHROUS MEMORY CONTROL
ECLKOUT
Y10
O/Z
IPD
ARE/SDCAS/ SSADS AOE/SDRAS/ SSOE AWE/SDWE/ SSWE ARDY
V11 W10 V12 Y5
O/Z O/Z O/Z I
IPU IPU IPU IPU
EA16 Y15 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
Terminal Functions (Continued)
SIGNAL NAME EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 ED15 ED14 ED13 ED12 ED11 ED10 ED9 PIN NO. PYP GFN W15 Y14 W14 V14 W13 V10 Y9 V9 Y8 W8 V8 W7 V7 Y6 EMIF - DATA N3 P3 P2 P1 R2 R3 T2 T1 U3 U1 U2 V1 V2 Y3 W4 V4 T19 T20 T18 R20 R19 P20 P18 I/O/Z IPU External data pins (ED[31:16] pins applicable to GFN package only) O/Z IPU External address (word address) TYPE IPD/ IPU EMIF - ADDRESS (CONTINUED) DESCRIPTION
PRODUCT PREVIEW
ED8 N20 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.)
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Terminal Functions (Continued)
SIGNAL NAME ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0 GP[4](EXT_INT4)/ AMUTEIN1 HD3/AMUTE1 HRDY/ACLKR1 HD6/AHCLKR1 HAS/ACLKX1 HD5/AHCLKX1 PIN NO. PYP GFN N19 N18 M20 M19 L19 L18 K19 K18 MULTICHANNEL AUDIO SERIAL PORT 1 (McASP1) C2 C20 H19 C17 E18 B18 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z IPU IPU IPU IPU IPU IPU General-purpose input/output pin 4 and external interrupt 4 (I/O/Z) [default] or McASP1 mute input (I/O/Z). Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (I/O/Z). Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z). Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master clock (I/O/Z). Host address strobe (I) [default] or McASP 1 transmit bit clock (I/O/Z). Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master clock (I/O/Z). Host half-word select - first or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK) (I/O/Z). Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/right clock (LRCLK) (I/O/Z). Host-port data pin 1 (I/O/Z) [ default] or McASP1 data pin 7 (I/O/Z). Host data strobe 1 (I) [default] or McASP1 data pin 6 (I/O/Z). Host data strobe 2 (I) [default] or McASP1 data pin 5 (I/O/Z). Host-port data pin 0 (I/O/Z) [ default] or McASP1 data pin 4 (I/O/Z). Host control - selects between control, address, or data registers (I) [default] or McASP1 data pin 3 (I/O/Z). Host chip select (I) [default] or McASP1 data pin 2 (I/O/Z). Host control - selects between control, address, or data registers (I) [default] or McASP1 data pin 1 (I/O/Z). I/O/Z IPU External data pins (ED[31:16] pins applicable to GFN package only) TYPE IPD/ IPU EMIF - DATA (CONTINUED) DESCRIPTION
HHWIL/AFSR1
H20
I/O/Z
IPU
HD2/AFSX1 HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1]
D18 D20 E19 F18 E20 G18 F20 G19
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
IPU IPU IPU IPU IPU IPU IPU IPU
HR/W/AXR1[0] G20 I/O/Z IPU Host read or write select (I) [default] or McASP1 data pin 0 (I/O/Z). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
Terminal Functions (Continued)
SIGNAL NAME GP[5](EXT_INT5)/ AMUTEIN0 CLKX1/AMUTE0 CLKR0/ACLKR0 TINP1/AHCLKX0 CLKX0/ACLKX0 CLKS0/AHCLKR0 FSR0/AFSR0 FSX0/AFSX0 PIN NO. PYP GFN TYPE IPD/ IPU DESCRIPTION
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) C1 L3 H3 F2 G3 K3 J3 H1 M3 M1 L2 F1 G2 G1 H2 J1 F1 F2 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z O I IPU IPD IPD IPD IPD IPD IPD IPD IPD IPD IPU IPD IPD IPD IPU IPU IPD IPD General-purpose input/output pin 5 and external interrupt 5 (I/O/Z) [default] or McASP0 mute input (I/O/Z). McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (I/O/Z). McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z). Timer 1 input (I) [default] or McBSP0 transmit high-frequency master clock (I/O/Z). McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z). McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0 receive high-frequency master clock (I/O/Z). McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z). McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z). McBSP1 receive frame sync (I/O/Z) [default] or McASP0 data pin 7 (I/O/Z). McBSP1 receive clock (I/O/Z) [default] or McASP0 data pin 6 (I/O/Z). McBSP1 rransmit data (O/Z) [default] or McASP0 data pin 5 (I/O/Z). Timer 1 output (O) [default] or McASP0 data pin 4 (I/O/Z). Timer 0 input (I) [default] or McASP0 data pin 3 (I/O/Z). Timer 0 output (O) [default] or McASP0 data pin 2 (I/O/Z). McBSP0 transmit data (O/Z) [default] or McASP0 data pin 1 (I/O/Z). McBSP0 receive data (I) [default] or McASP0 data pin 0 (I/O/Z). TIMER 1 TOUT1/AXR0[4] TINP1/AHCLKX0 Timer 1 output (O) [default] or McASP0 data pin 4 (I/O/Z). Timer 1 input (I) [default] or McBSP0 transmit high-frequency master clock (I/O/Z). TIMER0 TOUT0/AXR0[2] G1 O IPD Timer 0 output (O) [default] or McASP0 data pin 2 (I/O/Z). TINP0/AXR0[3] G2 I IPD Timer 0 input (I) [default] or McASP0 data pin 3 (I/O/Z). I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.)
PRODUCT PREVIEW
FSR1/AXR0[7] CLKR1/AXR0[6] DX1/AXR0[5] TOUT1/AXR0[4] TINP0/AXR0[3] TOUT0/AXR0[2] DX0/AXR0[1] DR0/AXR0[0]
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Terminal Functions (Continued)
SIGNAL NAME PIN NO. PYP GFN TYPE IPD/ IPU DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) CLKS1/SCL1 CLKR1/AXR0[6] CLKX1/AMUTE0 DR1/SDA1 DX1/AXR0[5] FSR1/AXR0[7] FSX1 E1 M1 L3 M2 L2 M3 L1 I I/O/Z I/O/Z I O/Z I/O/Z I/O/Z IPD IPD IPD IPU IPU IPD IPD McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock (I/O/Z). McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z). McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (I/O/Z). McBSP1 receive data (I) [default] or I2C1 data (I/O/Z). McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z). McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7 (I/O/Z). McBSP1 transmit frame sync McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0 receive high-frequency master clock (I/O/Z). McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z). McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z). McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z). McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z). McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z). McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z).
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0) CLKS0/AHCLKR0 CLKR0/ACLKR0 CLKX0/ACLKX0 DR0/AXR0[0] DX0/AXR0[1] FSR0/AFSR0 FSX0/AFSX0 K3 H3 G3 J1 H2 J3 H1 I I/O/Z I/O/Z I O/Z I/O/Z I/O/Z IPD IPD IPD IPU IPU IPD IPD
INTER-INTEGRATED CIRCUIT 1 (I2C1) CLKS1/SCL1 DR1/SDA1 SCL0 E1 M2 N1 I/O/Z I/O/Z I/O/Z IPD IPU IPU McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock (I/O/Z). McBSP1 receive data (I) [default] or I2C1 data (I/O/Z). I2C0 clock.
INTER-INTEGRATED CIRCUIT 0 (I2C0) SDA0 N2 I/O/Z IPU I2C0 data. I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
Terminal Functions (Continued)
SIGNAL NAME PIN NO. PYP GFN TYPE IPD/ IPU DESCRIPTION
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) HD15/GP[15] B14 IPU Host-port data pins (I/O/Z) [default] or general-purpose input/output pins (I/O/Z) * Used for transfer of data, address, and control * Also controls initialization of DSP modes at reset via pullup/pulldown resistors - Device Endian mode (HD8) 0 - Big Endian 1 - Little Endian - Boot mode (HD[4:3]) 00 - CE1 width 32-bit, HPI boot 01 - CE1 width 8-bit, Asynchronous external ROM boot with default timings (default mode) 10 - CE1 width 16 bit Asynchronous external ROM boot 16-bit, 11 - CE1 width 32-bit, Asynchronous external ROM boot - HPI_EN (HD14) 0 - HPI disabled, McASP1 and I2C0 enabled 1 - HPI enabled, McASP1 and I2C0 disabled (default) For device the F proper d i operation, th HD12 pin must b externally pulled d ti i t be t ll ll d down with a 1-k resistor. Other HD pins (HD [15, 13, 11:9, 7:5, 2:0] have pullups/pulldowns (IPUs/IPDs). ins ullu s/ ulldowns For proper device operation, do not oppose these pins with external IPUs/IPDs at reset. For more details, see the Device Configurations section of this data sheet. General-purpose input/output pins (I/O/Z) which also function as external interrupts [default] * Edge-driven * Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]) GP[4] and GP[5] pins also f d i l function as AMUTEIN1 M ASP1 mute i ti t input and td McASP1 AMUTEIN0 McASP0 mute input, respectively, if enabled by the INSTAT bit in the McASP AMUTE register. I/O/Z I/O/Z O I/O/Z IPU IPD IPU IPD Host-port data pin 7 (I/O/Z) [default] or general-purpose input/output 0 pin 3 (I/O/Z) Clock output at half of device speed (O/Z) [default] or this pin can be programmed as GP[2] pin. Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as a GP[1] pin (I/O/Z). Host-port data pin 4 (I/O/Z) [ default] or this pin can be programmed as a GP[0] pin (I/O/Z).
HD14/GP[14]
C14
IPU
HD13/GP[13]
A15
IPU
HD12/GP[12]
C15 I/O/Z
IPU
HD11/GP[11]
A16
IPU
PRODUCT PREVIEW
HD10/GP[10]
B16
IPU
HD9/GP[9]
C16
IPU
HD8/GP[8] GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/ AMUTEIN0 GP[4](EXT_INT4)/ AMUTEIN1 HD7/GP[3] CLKOUT2/GP[2] HINT/GP[1] HD4/GP[0]
B17 E3 D2 C1 I/O/Z
IPU
IPU
C2 A18 Y12 J20 C19
RESERVED FOR TEST RSV0 RSV1 A5 B5 O/Z A IPU Reserved. (Leave unconnected, do not connect to power or ground) Reserved. (Leave unconnected, do not connect to power or ground)
RSV2 D7 O/Z IPD Reserved. (Leave unconnected, do not connect to power or ground) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k resistor should be used.) A = Analog signal
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SPRS186 - DECEMBER 2001
Terminal Functions (Continued)
SIGNAL NAME PIN NO. PYP GFN A17 B3 B8 B13 C5 C10 D1 D16 D19 F3 H18 J2 R1 DVDD R18 T3 U5 U7 U12 U16 V13 V15 V19 W3 W9 W12 Y7 Y17 A9 A10 A12 B2 B19 C3 CVDD C7 C18 D5 D6 D11 D14 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground S 1 2 V supply voltage 1.2-V S 3 3 V supply voltage 3.3-V M18 TYPE SUPPLY VOLTAGE PINS DESCRIPTION
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
Terminal Functions (Continued)
SIGNAL NAME PIN NO. PYP GFN D15 F4 F17 K1 K4 K17 L4 L17 L20 R4 R17 U6 U10 U11 U14 U15 CVDD V3 V18 W2 W19 -- -- -- -- -- -- -- -- -- -- -- -- GROUND PINS A1 A2 A11 A14 VSS A19 A20 B1 B4 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground GND Ground pins S 1.2-V 1 2 V supply voltage TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED)
PRODUCT PREVIEW
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Terminal Functions (Continued)
SIGNAL NAME PIN NO. PYP GFN B11 B15 B20 C8 C9 D4 D8 D13 D17 E2 E4 E17 G4 G17 H4 H17 J4 K2 VSS K20 M4 M17 N4 N17 P4 P17 P19 T4 T17 U4 U8 U9 U13 U17 U20 W1 W5 W11 W16 I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground GND Ground pins ins F19 TYPE GROUND PINS (CONTINUED) DESCRIPTION
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
Terminal Functions (Continued)
SIGNAL NAME PIN NO. PYP GFN W20 Y1 Y2 Y13 Y19 Y20 -- -- -- VSS -- -- -- -- -- -- -- -- -- I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground GND Ground pins TYPE GROUND PINS (CONTINUED) DESCRIPTION
PRODUCT PREVIEW
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
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development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software needed to support any DSP application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug) EVM (Evaluation Module) The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320 DSP family member devices, including documentation. See this document for further information on TMS320 DSP documentation or any TMS320 DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320 DSP-related products from other companies in the industry. To receive TMS320 DSP literature, contact the Literature Response Center at 800/477-8924. For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and select "Find Development Tools". For device-specific tools, under "Semiconductor Products", select "Digital Signal Processors", choose a product family, and select the particular DSP device. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
Code Composer Studio, DSP/BIOS, XDS, and TMS320 are trademarks of Texas Instruments.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
device and development-support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification Fully qualified production device
TMP
TMS
Support tool development evolutionary flow:
PRODUCT PREVIEW
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification testing. Fully qualified development-support product
TMDS
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, GFN), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -225 is 225 MHz). Figure 11 provides a legend for reading the complete device name for any TMS320C6000 DSP family member.
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device and development-support tool nomenclature (continued) Table 32. TMS320C6713 Device Part Numbers (P/Ns) and Ordering Information
CORE and I/O VOLTAGE DEVICE ORDERABLE P/N C6713 TMS320C6713GFN225 TMS320C6713GFN150 TMS320C6713PYP150 225 MHz/1350 MFLOPS 150 MHz/900 MFLOPS 150 MHz/900 MFLOPS 1.2 V 1.2 V 1.2 V 3.3 V 3.3 V 3.3 V 0_C to 90_C 0_C to 90_C 0_C to 90_C DEVICE SPEED CVDD (CORE) DVDD (I/O) OPERATING CASE TEMPERATURE RANGE
TMS 320 PREFIX TMX = Experimental device TMP = Prototype device TMS = Qualified device SMJ = MIL-PRF-38535, QML SM = High Rel (non-38535)
C
6713
GFN
()
225 DEVICE SPEED RANGE 225 MHz 100 MHz 233 MHz 120 MHz 250 MHz 150 MHz 300 MHz 167 MHz 400 MHz 200 MHz 500 MHz 600 MHz
DEVICE FAMILY 320 = TMS320 DSP family
TEMPERATURE RANGE (DEFAULT: 0C TO 90C) Blank = 0C to 90C, commercial temperature A = -40C to 105C, extended temperature PACKAGE TYPE GFN = 256-pin plastic BGA GGP = 352-pin plastic BGA GJC = 352-pin plastic BGA GJL = 352-pin plastic BGA GLS = 384-pin plastic BGA GLW = 340-pin plastic BGA GNY = 384-pin plastic BGA GNZ = 352-pin plastic BGA GHK = 288-pin plastic MicroStar BGAt PYP = 208-pin PowerPADt plastic QFP DEVICE C6000 DSP: 6201 6202 6202B 6203B 6203C
TECHNOLOGY C = CMOS
6204 6205 6211 6211B
6414 6415 6416 6701
6711 6711B 6712 6713
BGA = QFP =
Ball Grid Array Quad Flatpack
Figure 11. TMS320C6000 DSP Device Nomenclature (Including the TMS320C6713 Device)
MicroStar BGA and PowerPAD are trademarks of Texas Instruments.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
documentation support
Extensive documentation supports all TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user's reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000 DSP devices: The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts. The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the peripherals available on the C6000 DSP platform of devices, such as the external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and power-down modes. This guide also includes information on internal data and program memories. The PowerPAD Thermally Enhanced Package Technical brief (literature number SLMA002) focuses on the specifics of integrating a PowerPAD package into the printed circuit board design to make optimum use of the thermal efficiencies designed into the PowerPAD package.
PRODUCT PREVIEW
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x devices, associated development tools, and third-party support. The tools support documentation is electronically available within the Code Composer Studio Integrated Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). See the Worldwide Web URL for the application report How To Begin Development Today with the TMS320C6713 Floating-Point DSP (literature number SPRA809), which describes in more detail the similarities/differences between the C6713 and C6711 C6000 DSP devices.
C62x is a trademark of Texas Instruments.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
clock generator, oscillator, and PLL
The TMS320C6713 includes a flexible clock generator module consisting of a PLL and oscillator, with several dividers so that different clocks may be generated for different parts of the system (i.e., DSP core, Internal Peripheral Control, External Memory Interface - EMIF, and Audio Peripheral Serial Clocks). Figure 12 illustrates the PLL and clock generator logic.
+1.2 V 50 R 0.1 F 50 R CLKMODE0 CLKIN 470 pF CVDD OSCIN 470 pF OSCOUT VSS
OSCDIV1
PLLV 0.01 F PLLG
PLLOUT
PLLREF
DIVIDER D0
PLLEN PLL x1, x2, ..., x16
DIVIDER D1

1 0 Osc.
/1, /2, ..., /32
DIVIDER D2
/1, /2, ..., /32
DIVIDER D3
CLKOUT3 For Use in System ECLKIN
/1, /2, ..., /32
AUXCLK (Internal Clock Source to McASP0 and McASP1)
SYSCLK2 (Peripherals Bus and CLKOUT2) SYSCLK3
/1, /2, ..., /32
(EMIF Clock Input)
10
EKSRC Bit (DEVCFG.[4])
C6713 DSP Exact values for these components depend on choice of crystal
EMIF
ECLKOUT
Figure 12. PLL and Clock Generator Logic The clock may be sourced either from an externally generated 3.3-V clock input on the CLKIN pin, or from the on-chip oscillator if an external crystal circuit is attached to the device. The oscillator supports fundamental mode crystals up to 30 MHz. This reference clock (AUXCLK) is also directly available to the McASP modules for use as an internal serial port clock; and may be divided down by a programmable divider (/1, /2, /3, ..., /32) and output on the CLKOUT3 pin for other use in the system. The input clock source may then either be divided down (by /1, /2, ..., /32) and then multiplied up by a factor of x1, x2, x3, and so on, up to x16. Either the input clock or the PLL output (if PLLEN is selected) then serves as the high-frequency reference clock for the rest of the DSP system. The DSP core clock, the peripheral bus control clock, and the EMIF clock may be divided down from this high-frequency clock (each with a unique divider) . For example, with a 30 MHz input if the PLL output is configured for 450 MHz, the DSP core may be operated at 225 MHz (/2) while the EMIF may be configured to operate at a rate of 75 MHz (/6).
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PRODUCT PREVIEW
1 0
/1, /2, ..., /32
SYSCLK1 (DSP Core Clock)
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
clock generator, oscillator, and PLL (continued)
The EMIF itself may be clocked from a totally unrelated (asynchronous) reference clock input on the ECLKIN pin if a specific EMIF frequency is needed, or from the on-chip clock generation logic. The settings for the PLL multiplier and each of the dividers in the clock generation block may be reconfigured via software at run time. If either the input to the PLL is changed or if the PLL multiplier is changed, then software must enter bypass first and stay in bypass until the PLL has had enough time to lock (see electrical specifications). The clock generator has dedicated power supply pins, and it is recommended that these pins be filtered with a pair of 50R ferrite beads in series with each supply line, bypassed with a pair of capacitors (0.1 F and 0.01 F) as close to the device pins (PLLV, PLLG) as possible (as shown in Figure 12). Similarly, for the lowest jitter on the oscillator circuit, it is recommended that a pair of 470-pF capacitors be connected between an isolated (not directly connected to the board supply) CVDD and VSS pin on either side of the oscillator. This helps to cancel out switching noise from other circuits on the DSP device. Note that there is a specific minimum and maximum input clock for the block labeled PLL in Figure 12, as well as for the DSP core, peripheral control, and EMIF. In addition, there is a maximum output frequency for the PLL. The clock generator must not be configured to exceed any of these constraints (certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported). SYSCLK2 is the internal clock source for peripheral bus control. SYSCLK2 (Divider D2) must be programmed to be half of the SYSCLK1 rate. For example, if D1 is configured to divide-by-2 mode (/2), then D2 must be programmed to divide-by-4 mode (/4). SYSCLK2 is also tied directly to CLKOUT2 pin (see Figure 12). For detailed information on the clock generator (PLL and oscillator registers) and their associated software bit descriptions, see Table 33 through Table 36.
PRODUCT PREVIEW
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
clock generator, oscillator, and PLL (continued)
PLLCSR Register (0x01B7 C100)
31 28 27 24 23 Reserved R-0 15 12 11 8 7 6 STABLE RW-0 5 4 Reserved R-0 3 PLLRST RW-1 2 1 PLLPWRDN R/W-0b PLLEN RW-0 0 20 19 16
Reserved R-0
-
R-0
Legend: R = Read only, R/W = Read/Write; -n = value after reset
Table 33. PLL Control/Status Register (PLLCSR)
BIT # 31:7 6 5:4 3 2 1 NAME Reserved STABLE Reserved PLLRST Reserved PLLPWRDN DESCRIPTION Reserved. Read-only, writes have no effect. Oscillator Input Stable. This bit indicates if the OSCIN/CLKIN input has stabilized. 0 - OSCIN/CLKIN input not yet stable. Oscillator counter is not finished counting (default). 1 - OSCIN/CLKIN input stable. Reserved. Read-only, writes have no effect. Asserts RESET to PLL 0 - PLL Reset Released. 1 - PLL Reset Asserted (default). Reserved. Read-only, writes have no effect. Select PLL Power Down 0 - PLL Operational (default). 1 - PLL Placed in Power-Down State. PLL Mode Enable 0 - Bypass Mode (default). PLL disabled. Divider D0 and PLL are bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down directly from input reference clock. 1 - PLL Enabled. Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down from PLL output.
0
PLLEN
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
clock generator, oscillator, and PLL (continued)
PLLM Register (0x01B7 C110)
31 28 27 24 23 Reserved R-0 15 12 11 Reserved R-0 Legend: R = Read only, R/W = Read/Write; -n = value after reset 8 7 6 5 4 3 2 PLLM R/W-0 0111 1 0 20 19 16
Table 34. PLL Multiplier Control Register (PLLM)
BIT # 31:5 NAME Reserved DESCRIPTION Reserved. Read-only, writes have no effect. PLL multiply mode [default is x8 (0 0111)]. 00000 = x1 01000 = x9 00001 = x2 01001 = x10 00010 = x3 01010 = x11 00011 = x4 01011 = x12 00100 = x5 01100 = x13 00101 = x6 01101 = x14 00110 = x7 01110 = x15 00111 = x8 01111 = x16 PLLM select values 10000 through 11111 are not supported.
PRODUCT PREVIEW
4:0
PLLM
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
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clock generator, oscillator, and PLL (continued)
PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 Registers (0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively)
31 28 27 24 23 Reserved R-0 15 14 12 11 Reserved R-0 8 7 5 4 3 2 PLLDIVx R/W-x xxxx 1 0 20 19 16
DxEN
R/W-1
Legend: R = Read only, R/W = Read/Write; -n = value after reset Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1 (0 0000), /1 (0 0000), /2 (0 0001), and /2 (0 0001), respectively.
Table 35. PLL Wrapper Divider x Registers (Prescaler D0 and Dividers D1, D2, and D3)
BIT # 31:16 15 14:5 NAME Reserved DxEN Reserved DESCRIPTION Reserved. Read-only, writes have no effect. Divider Dx Enable (where x denotes 0 through 3). 0 - Divider x Disabled. No clock output. 1 - Divider x Enabled (default). Reserved. Read-only, writes have no effect. PLL Divider Ratio [Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1, /1, /2, and /2, respectively]. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 = = = = = = = = = = = = = = = = /1 /2 /3 /4 /5 /6 /7 /8 /9 /10 /11 /12 /13 /14 /15 /16 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 = = = = = = = = = = = = = = = = /17 /18 /19 /20 /21 /22 /23 /24 /25 /26 /27 /28 /29 /30 /31 /32
4:0
PLLDIVx
Note that SYSCLK2 must run at half the rate of SYSCLK1. Therefore, the divider ratio of D2 must be two times slower than D1. For example, if D1 is set to /2, then D2 must be set to /4.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
clock generator, oscillator, and PLL (continued)
OSCDIV1 Register (0x01B7 C124)
31 28 27 24 23 Reserved R-0 15 14 12 11 Reserved R-0 8 7 5 4 3 2 OSCDIV1 R/W-0 0111 1 0 20 19 16
OD1EN
R/W-1
Legend: R = Read only, R/W = Read/Write; -n = value after reset
The OSCDIV1 register controls the oscillator divider 1 for CLKOUT3. The CLKOUT3 signal does not go through the PLL path. Table 36. Oscillator Divider 1 Register (OSCDIV1)
BIT # NAME Reserved OD1EN Reserved DESCRIPTION Reserved. Read-only, writes have no effect. Oscillator Divider 1 Enable. 0 - Oscillator Divider 1 Disabled. 1 - Oscillator Divider 1 Enabled (default). Reserved. Read-only, writes have no effect. Oscillator Divider 1 Ratio [default is /8 (0 0111)]. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 = = = = = = = = = = = = = = = = /1 /2 /3 /4 /5 /6 /7 /8 /9 /10 /11 /12 /13 /14 /15 /16 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 = = = = = = = = = = = = = = = = /17 /18 /19 /20 /21 /22 /23 /24 /25 /26 /27 /28 /29 /30 /31 /32
PRODUCT PREVIEW
31:16 15 14:5
4:0
OSCDIV1
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, CVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 1.35 V Supply voltage range, DVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.5 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.5 V Operating case temperature ranges, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65_C to 150_C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN CVDD DVDD V(C - D) V(D - C) VIH VIL Supply voltage, Core referenced to VSS Supply voltage, I/O referenced to VSS Maximum supply voltage difference CVDD - DVDD Maximum supply voltage difference DVDD - CVDD High-level input voltage Low-level input voltage All signals except TDO, EMU[5:0], ECLKOUT, CLKOUT2, CLKOUT3, SCL1, SDA1, SCL0, and SDA0 TDO, EMU[5:0], ECLKOUT, CLKOUT2, and CLKOUT3 All signals except TDO, EMU[5:0], ECLKOUT, CLKOUT2, CLKOUT3, SCL1, SDA1, SCL0, and SDA0 IOL Low-level output current TDO, EMU[5:0], ECLKOUT, CLKOUT2, and CLKOUT3 SCL1, SDA1, SCL0, and SDA0 0.7*DVDD 0.3*DVDD -8 1.14 3.13 NOM 1.2 3.3 MAX 1.26 3.47 1.32 2.75 UNIT V V V V V V mA
IOH
High-level out ut current output
-16
mA
8
mA
16 6
mA mA
TC Operating case temperature 0 90 _C The core supply should be powered up at the same time as, or prior to (and powered down after), the I/O supply. Systems should be designed to ensure that neither supply is powered up for an extended period of time if the other supply is below the proper operating voltage.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)
PARAMETER All signals except TDO, EMU[5:0], ECLKOUT, CLKOUT2, CLKOUT3, SCL1, SDA1, SCL0, and SDA0 TDO, EMU[5:0], ECLKOUT, CLKOUT2, and CLKOUT3 All signals except TDO, EMU[5:0], ECLKOUT, CLKOUT2, CLKOUT3, SCL1, SDA1, SCL0, and SDA0 VOL Low-level output voltage lt TDO, EMU[5:0], ECLKOUT, CLKOUT2, and CLKOUT3 TEST CONDITIONS MIN 0.8*DVDD 2.4 TYP MAX UNIT V
VOH
High-level output voltage lt
DVDD = MIN, IOH = MAX
V
DVDD = MIN, IOL = MAX
0.22*DVDD 0.4
V
V V V uA uA
SCL1 SDA1 SCL0 and SDA0 SCL1, SDA1, SCL0,
DVDD = MIN, IOL = 3 mA DVDD = MIN, IOL = 6 mA VI = VSS to DVDD VO = DVDD or 0 V C6713, CVDD = NOM, CPU clock = 225 MHz C6713, CVDD = NOM, CPU clock = 225 MHz C6713, DVDD = NOM, CPU clock = 225 MHz
0.4 0.6 150 10
II
Input current Off-state output current Supply current, CPU + CPU memory access Supply current, peripherals Supply current, I/O pins Input capacitance
PRODUCT PREVIEW
IOZ
IDD2V
TBD
mA
IDD2V IDD3V Ci
TBD TBD TBD
mA mA pF
Co Output capacitance TBD pF For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. Measured with average activity (50% high/50% low power). For more details on CPU, peripheral, and I/O activity, refer to the TMS320C6000 Power Consumption Summary application report (literature number SPRA486).
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SPRS186 - DECEMBER 2001
PARAMETER MEASUREMENT INFORMATION
IOL Tester Pin Electronics 50 Output Under Test
Vcomm
CT IOH Where: IOL IOH Vcomm CT = = = = 2 mA 2 mA 0.8 V 10-15-pF typical load-circuit capacitance
Figure 13. Test Load Circuit for AC Timing Measurements
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.
Vref = 1.5 V
Figure 14. Input and Output Voltage Reference Levels for ac Timing Measurements All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, and VOL MAX and VOH MIN for output clocks.
Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
Figure 15. Rise and Fall Transition Time Voltage Reference Levels
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameters and board routing analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers may be used to compensate any timing differences. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 37 and Figure 16). Figure 16 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device.
PRODUCT PREVIEW
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PARAMETER MEASUREMENT INFORMATION (CONTINUED)
Table 37. IBIS Timing Parameters Example (see Figure 16)
NO. 1 2 3 4 5 6 7 8 9 10 11 DESCRIPTION Clock route delay Minimum DSP hold time Minimum DSP setup time External device hold time requirement External device setup time requirement Control signal route delay External device hold time External device access time DSP hold time requirement DSP setup time requirement Data route delay
ECLKOUT (Output from DSP) 1 ECLKOUT (Input to External Device) Control Signals (Output from DSP) 3 4 5 Control Signals (Input to External Device) Data Signals (Output from External Device) Data Signals (Input to DSP) Control signals include data for Writes. Data signals are generated during Reads from an external device. 6 7 8 2
10 11
9
Figure 16. IBIS Input/Output Timings
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
INPUT AND OUTPUT CLOCKS timing requirements for CLKIN (see Figure 17)
NO. 1 2 3 tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN low -150 -225 MIN MAX ns ns ns ns UNIT
4 Transition time, CLKIN The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. C = CLKIN cycle time in ns. For example, when CLKIN frequency is 40 MHz, use C = 25 ns.
1 2 CLKIN
4
PRODUCT PREVIEW
3 4
Figure 17. CLKIN Timings
switching characteristics over recommended operating conditions for CLKOUT2 (see Figure 18)
NO. 1 2 3 tc(CKO2) tw(CKO2H) tw(CKO2L) tt(CKO2) Cycle time, CLKOUT2 Pulse duration, CLKOUT2 high Pulse duration, CLKOUT2 low PARAMETER MIN -150 -225 MAX ns ns ns ns UNIT
4 Transition time, CLKOUT2 The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. P = 1/CPU clock frequency in ns 1 2 CLKOUT2 3 4
4
Figure 18. CLKOUT2 Timings
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SPRS186 - DECEMBER 2001
INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT3 (see Figure 19)
NO. 1 2 3 tc(CKO3) tw(CKO3H) tw(CKO3L) tt(CKO3) Cycle time, CLKOUT3 Pulse duration, CLKOUT3 high Pulse duration, CLKOUT3 low PARAMETER MIN -150 -225 MAX ns ns ns ns UNIT
4 Transition time, CLKOUT3 The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. P = 1/CPU clock frequency in ns 1 2 CLKOUT3 3 4
4
Figure 19. CLKOUT3 Timings
timing requirements for ECLKIN (see Figure 20)
NO. 1 2 3 tc(EKI) tw(EKIH) tw(EKIL) tt(EKI) Cycle time, ECLKIN Pulse duration, ECLKIN high Pulse duration, ECLKIN low -150 -225 MIN MAX ns ns ns ns UNIT
4 Transition time, ECLKIN The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. 1 2 ECLKIN 3 4 4
Figure 20. ECLKIN Timings
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for ECLKOUT (see Figure 21)
NO. 1 2 3 4 5 6 tc(EKO) tw(EKOH) tw(EKOL) tt(EKO) td(EKIH-EKOH) td(EKIL-EKOL) PARAMETER Cycle time, ECLKOUT Pulse duration, ECLKOUT high Pulse duration, ECLKOUT low Transition time, ECLKOUT Delay time, ECLKIN high to ECLKOUT high -150 -225 MIN MAX UNIT
Delay time, ECLKIN low to ECLKOUT low The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN. E = ECLKIN period in ns EH is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns.
PRODUCT PREVIEW
ECLKIN 6 5 ECLKOUT 2 1 3
4
4
Figure 21. ECLKOUT Timings
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SPRS186 - DECEMBER 2001
ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles (see Figure 22-Figure 23)
NO. 3 4 6 7 tsu(EDV-AREH) th(AREH-EDV) tsu(ARDY-EKOH) th(EKOH-ARDY) Setup time, EDx valid before ARE high Hold time, EDx valid after ARE high Setup time, ARDY valid before ECLKOUT high Hold time, ARDY valid after ECLKOUT high -150 -225 MIN MAX UNIT
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. E = ECLKOUT period in ns
switching characteristics over recommended operating conditions for asynchronous memory cycles (see Figure 22-Figure 23)
NO. 1 2 5 8 9 10 tosu(SELV-AREL) toh(AREH-SELIV) td(EKOH-AREV) tosu(SELV-AWEL) toh(AWEH-SELIV) td(EKOH-AWEV) PARAMETER Output setup time, select signals valid to ARE low Output hold time, ARE high to select signals invalid Delay time, ECLKOUT high to ARE vaild Output setup time, select signals valid to AWE low Output hold time, AWE high to select signals invalid -150 -225 MIN MAX UNIT
Delay time, ECLKOUT high to AWE vaild RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. E = ECLKOUT period in ns Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0].
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 ECLKOUT 1 CEx 1 BE[3:0] 1 EA[21:2] Address 3 4 ED[31:0] 1 AOE/SDRAS/SSOE 5 ARE/SDCAS/SSADS AWE/SDWE/SSWE 6 ARDY AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. Read Data 2 5 BE 2 2 2 Strobe = 3 Not Ready Hold = 2
PRODUCT PREVIEW
7 6
7
Figure 22. Asynchronous Memory Read Timing
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ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 ECLKOUT 8 CEx 8 BE[3:0] 8 EA[21:2] 8 ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS 10 AWE/SDWE/SSWE 7 6 ARDY AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. 6 7 10 Write Data Address 9 BE 9 9 9 Strobe = 3 Not Ready Hold = 2
Figure 23. Asynchronous Memory Write Timing
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (see Figure 24)
NO. 6 tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read EDx valid before ECLKOUT high -150 -225 MIN MAX UNIT
7 Hold time, read EDx valid after ECLKOUT high The C6713 SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles (see Figure 24 and Figure 25)
NO. 1 td(EKOH-CEV) td(EKOH-BEV) td(EKOH-BEIV) td(EKOH-EAV) td(EKOH-EAIV) td(EKOH-ADSV) td(EKOH-OEV) td(EKOH-EDV) td(EKOH-EDIV) td(EKOH-WEV) PARAMETER Delay time, ECLKOUT high to CEx valid Delay time, ECLKOUT high to BEx valid Delay time, ECLKOUT high to BEx invalid Delay time, ECLKOUT high to EAx valid Delay time, ECLKOUT high to EAx invalid Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid Delay time, ECLKOUT high to EDx valid Delay time, ECLKOUT high to EDx invalid -150 -225 MIN MAX UNIT
PRODUCT PREVIEW
2 3 4 5 8 9 10 11 12
Delay time, ECLKOUT high to AWE/SDWE/SSWE valid The C6713 SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
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SPRS186 - DECEMBER 2001
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
ECLKOUT 1 CEx BE[3:0] EA[21:2] 6 ED[31:0] 8 ARE/SDCAS/SSADS 9 AOE/SDRAS/SSOE AWE/SDWE/SSWE ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. 9 8 Q1 2 BE1 4 EA 7 Q2 Q3 Q4 3 BE2 BE3 5 BE4 1
Figure 24. SBSRAM Read Timing
ECLKOUT 1 CEx 2 BE1 4 EA[21:2] 10 Q1 8 ARE/SDCAS/SSADS AOE/SDRAS/SSOE 12 AWE/SDWE/SSWE 12 8 EA 11 Q2 Q3 Q4 3 BE2 BE3 5 BE4 1
BE[3:0]
ED[31:0]
ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 25. SBSRAM Write Timing
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 26)
NO. 6 7 tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read EDx valid before ECLKOUT high -150 -225 MIN MAX UNIT
Hold time, read EDx valid after ECLKOUT high The C6713 SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous DRAM cycles (see Figure 26-Figure 32)
NO. 1 td(EKOH-CEV) td(EKOH-BEV) td(EKOH-BEIV) td(EKOH-EAV) td(EKOH-EAIV) td(EKOH-CASV) td(EKOH-EDV) td(EKOH-EDIV) td(EKOH-WEV) td(EKOH-RAS) PARAMETER Delay time, ECLKOUT high to CEx valid Delay time, ECLKOUT high to BEx valid Delay time, ECLKOUT high to BEx invalid Delay time, ECLKOUT high to EAx valid Delay time, ECLKOUT high to EAx invalid Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid Delay time, ECLKOUT high to EDx valid Delay time, ECLKOUT high to EDx invalid Delay time, ECLKOUT high to AWE/SDWE/SSWE valid -150 -225 MIN MAX UNIT
PRODUCT PREVIEW
2 3 4 5 8 9 10 11
12 Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid The C6713 SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts, but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow. ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
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SPRS186 - DECEMBER 2001
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ ECLKOUT 1 CEx BE[3:0] 4 Bank 4 Column 4 EA12 6 ED[31:0] AOE/SDRAS/SSOE 8 ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 8 D1 7 D2 D3 D4 2 BE1 5 3 BE2 BE3 BE4 1
EA[21:13] EA[11:2]
5
5
Figure 26. SDRAM Read Command (CAS Latency 3)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
SYNCHRONOUS DRAM TIMING (CONTINUED)
WRITE ECLKOUT 1 CEx 2 BE[3:0] 4 EA[21:13] 4 EA[11:2] 4 EA12 9 ED[31:0] D1 9 D2 D3 D4 10 Column 5 Bank 5 BE1 5 4 BE2 BE3 BE4 3 2
PRODUCT PREVIEW
AOE/SDRAS/SSOE 8 ARE/SDCAS/SSADS 11 AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 11 8
Figure 27. SDRAM Write Command
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SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV ECLKOUT 1 CEx BE[3:0] 4 Bank Activate 4 Row Address 4 Row Address 5 1
EA[21:13] EA[11:2]
5
5
EA12 ED[31:0]
12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE
12
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
Figure 28. SDRAM ACTV Command
DCAB ECLKOUT 1 CEx BE[3:0] EA[21:13, 11:2] 4 EA12 ED[31:0] 12 AOE/SDRAS/SSOE ARE/SDCAS/SSADS 11 AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 11 12 5 1
Figure 29. SDRAM DCAB Command
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
SYNCHRONOUS DRAM TIMING (CONTINUED)
DEAC ECLKOUT 1 CEx BE[3:0] 4 EA[21:13] EA[11:2] 4 EA12 ED[31:0] 12 AOE/SDRAS/SSOE 12 5 Bank 5 1
PRODUCT PREVIEW
ARE/SDCAS/SSADS 11 AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 11
Figure 30. SDRAM DEAC Command
REFR ECLKOUT 1 CEx BE[3:0] EA[21:2] EA12 ED[31:0] 12 AOE/SDRAS/SSOE 8 ARE/SDCAS/SSADS AWE/SDWE/SSWE ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. 8 12 1
Figure 31. SDRAM REFR Command
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SPRS186 - DECEMBER 2001
SYNCHRONOUS DRAM TIMING (CONTINUED)
MRS ECLKOUT 1 CEx BE[3:0] 4 MRS value 5 1
EA[21:2] ED[31:0]
12 AOE/SDRAS/SSOE 8 ARE/SDCAS/SSADS 11 AWE/SDWE/SSWE
12
8
11
ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
Figure 32. SDRAM MRS Command
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles (see Figure 33)
NO. 3 toh(HOLDAL-HOLDL) E = ECLKIN period in ns Output hold time, HOLD low after HOLDA low -150 -225 MIN MAX UNIT
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles (see Figure 33)
NO. 1 2 4 td(HOLDL-EMHZ) td(EMHZ-HOLDAL) td(HOLDH-EMLZ) td(EMLZ-HOLDAH) PARAMETER Delay time, HOLD low to EMIF Bus high impedance Delay time, EMIF Bus high impedance to HOLDA low Delay time, HOLD high to EMIF Bus low impedance -150 -225 MIN MAX UNIT
PRODUCT PREVIEW
5 Delay time, EMIF Bus low impedance to HOLDA high E = ECLKIN period in ns EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE. All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. DSP Owns Bus External Requestor Owns Bus 3 HOLD 2 HOLDA EMIF Bus 1 C6713 4 C6713 5 DSP Owns Bus
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
Figure 33. HOLD/HOLDA Timing
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
BUSREQ TIMING switching characteristics over recommended operating conditions for the BUSREQ cycles (see Figure 34)
NO. 1 td(EKOH-BUSRV) PARAMETER Delay time, ECLKOUT high to BUSREQ valid -150 -225 MIN MAX UNIT
ECLKOUT
1 BUSREQ
1
Figure 34. BUSREQ Timing
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
RESET TIMING timing requirements for reset (see Figure 35)
NO. Width of the RESET pulse (PLL stable) 1 14 tw(RST) tsu(HD) th(HD) Width of the RESET pulse (PLL needs to sync up) Setup time, HD boot configuration bits valid before RESET high Hold time, HD boot configuration bits valid after RESET high -150 -225 MIN MAX UNIT
15 P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4 when CLKIN and PLL are stable. This parameter applies to CLKMODE x4 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may need up to 250 s to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock generator, oscillator, and PLL section for PLL lock times. Boot and device configurations consist of: HD[15:12, 8, 4:3].
switching characteristics over recommended operating conditions during reset#|| (see Figure 35)
PRODUCT PREVIEW
NO. 2 3 4 5 6 7 8 9 10 11 12 13 td(RSTL-ECKI) td(RSTH-ECKI) td(RSTL-EMIFZHZ) td(RSTH-EMIFZV) td(RSTL-EMIFHIV) td(RSTH-EMIFHV) td(RSTL-EMIFLIV) td(RSTH-EMIFLV) td(RSTL-HIGHIV) td(RSTH-HIGHV) td(RSTL-ZHZ) td(RSTH-ZV)
PARAMETER Delay time, RESET low to ECLKIN synchronized internally Delay time, RESET high to ECLKIN synchronized internally Delay time, RESET low to EMIF Z group high impedance Delay time, RESET high to EMIF Z group valid Delay time, RESET low to EMIF high group invalid Delay time, RESET high to EMIF high group valid Delay time, RESET low to EMIF low group invalid Delay time, RESET high to EMIF low group valid Delay time, RESET low to high group invalid Delay time, RESET high to high group valid Delay time, RESET low to Z group high impedance Delay time, RESET high to Z group valid
-150 -225 MIN MAX
UNIT
P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. # E = ECLKIN period in ns || EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE EMIF high group consists of: HOLDA EMIF low group consists of: BUSREQ High group consists of: HRDY/ACLKR1 and HINT/GP[1] Z group consists of: HD[11:9, 7:5, 2:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, TOUT0, and TOUT1.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
RESET TIMING (CONTINUED)
CLKOUT2 1 RESET 2 ECLKIN 4 EMIF Z Group 6 EMIF High Group 8 EMIF Low Group 10 High Group 14 15 Z Group Boot and Device Configurations EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE HOLDA BUSREQ HRDY/ACLKR1 and HINT/GP[1] HD[11:9, 7:5, 2:0], CLKX0/ACLKX0, CLKX1/AMUTE0, FSX0/AFSX0, FSX1, DX0/AXR0[1], DX1/AXR0[5], CLKR0/ACLKR0, CLKR1/AXR0[6], FSR0/AFSR0, FSR1/AXR0[7], TOUT0/AXR0[2], and TOUT1/AXR0[4]. Boot and device configurations consist of: HD[15:12, 8, 4:3]. EMIF Z group consists of: EMIF high group consists of: EMIF low group consists of: High group consists of: Z group consists of: 12 11 13 9 7 5 3
Figure 35. Reset Timing
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
EXTERNAL INTERRUPT TIMING timing requirements for external interrupts (see Figure 36)
NO. 1 2 tw(ILOW) tw(IHIGH) Width of the interrupt pulse low -150 -225 MIN Width of the interrupt pulse high P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. 2 MAX UNIT
1 EXT_INT, NMI
Figure 36. External/NMI Interrupt Timing
PRODUCT PREVIEW
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING timing requirements for McASP (see Figure 37 and Figure 38)
NO. 1 2 3 4 5 6 7 8 tc(AHCKRX) tw(AHCKRX) tc(CKRX) tw(CKRX) tsu(FRXC-KRX) th(CKRX-FRX) tsu(AXR-CKRX) th(CKRX-AXR) Cycle time, AHCLKR/X Pulse duration, AHCLKR/X high or low ACLKR/X int Cycle time ACLKR/X time, Pulse duration ACLKR/X high or low duration, Setup time AFSR/X input valid before ACLKR/X latches data time, Hold time AFSR/X input valid after ACLKR/X latches data time, Setup time AXR input valid before ACLKR/X latches data time, Hold time AXR input valid after ACLKR/X latches data time, ACLKR/X ext ACLKR/X int ACLKR/X ext ACLKR/X int ACLKR/X ext ACLKR/X int ACLKR/X ext ACLKR/X ext ACLKR/X int ACLKR/X ext ACLKR/X int -150 -225 MIN MAX UNIT
switching characteristics over recommended operating conditions for McASP (see Figure 37 and Figure 38)
NO. 9 10 11 12 13 14 15 16 tc(AHCKRX) tw(AHCKRX) tc(CKRX) tw(CKRX) td(CKRX-FRX) td(CKRX-AXR1V) td(CKRX-AXRV) tdis(CKRX-AXRHZ) PARAMETER Cycle time, AHCLKR/X Pulse duration, AHCLKR/X high or low ACLKR/X int Cycle time ACLKR/X time, Pulse duration ACLKR/X high or low duration, Delay time ACLKR/X transmit edge to AFSX/R output valid time, Delay time ACLKR/X transmit edge to AXR first bit valid time, Delay time ACLKR/X transmit edge to AXR output valid time, Disable time, AXR high im edance following last data bit from impedance ACLKR/X transmit edge ACLKR/X ext ACLKR/X int ACLKR/X ext ACLKR/X int ACLKR/X ext ACLKR/X int ACLKR/X ext ACLKR/X int ACLKR/X ext ACLKR/X int ACLKR/X ext -150 -225 MIN MAX UNIT
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED)
2 1 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 4 3 ACLKR/X (Falling Edge Polarity) ACLKR/X (Rising Edge Polarity) 6 5 AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) 8 7 AXR[n] (Data In/Receive) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 4 2
PRODUCT PREVIEW
Figure 37. McASP Input Timings
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SPRS186 - DECEMBER 2001
MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED)
10 9 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) 12 12 10
11 ACLKR/X (Falling Edge Polarity) ACLKR/X (Rising Edge Polarity)
13 13 AFSR/X (Bit Width, 0 Bit Delay)
13 13
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay) 13 AFSR/X (Slot Width, 0 Bit Delay) 13 13
AFSR/X (Slot Width, 1 Bit Delay) 15 AFSR/X (Slot Width, 2 Bit Delay) 14 AXR[n] (Data Out/Transmit) A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 15 15 15 15 15 16
Figure 38. McASP Output Timings
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
INTER-INTEGRATED CIRCUITS (I2C) TIMING switching characteristics for I2C timings (see Figure 39)
-150 -225 NO. STANDARD MODE MIN 1 2 3 4 5 6 7 tc(SCL) tw(SCLL) tw(SCLH) tsu(SCLH-SDAL) th(SCLL-SDAL) tsu(SDA-SDLH) th(SDA SDLL) h(SDA-SDLL) tw(SDAH) tr(SDA) tr(SCL) tf(SDA) tf(SCL) tsu(SCLH-SDAH) tw(SP) Cb Cycle time, SCL Pulse duration, SCL low Pulse duration, SCL high Setup time, SCL high before SDA low (for a repeated START condition) Hold time, SCL low after SDA low (for a repeated START condition) Setup time, SDA valid before SCL high Hold time, SDA valid after SCL low For CBUS compatible masters For I2C bus devices MAX FAST MODE MIN MAX UNIT
PRODUCT PREVIEW
8 9 10 11 12 13 14 15
Pulse duration, SDA high between STOP and START conditions Rise time, SDA Rise time, SCL Fall time, SDA Fall time, SCL Setup time, SCL high before SDA high (for STOP condition) Pulse duration, spike (must be suppressed) Capacitive load for each bus line
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. The maximum th(SCLL-SDAL) has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal. Cb = The total capacitance of one bus line in pF. SDA 8 2 10 SCL 1 7 5 Stop NOTES: A. B. C. Start 12 5 4 3 6 14 13
D.
Repeated Stop Start A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum th(SCLL-SDAL) has only to be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL signal. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SDLH) * 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SDLH) = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released. Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed
Figure 39. I2C Timings
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
HOST-PORT INTERFACE TIMING timing requirements for host-port interface cycles (see Figure 40, Figure 41, Figure 42, and Figure 43)
NO. 1 2 3 4 10 11 12 13 14 18 tsu(SELV-HSTBL) th(HSTBL-SELV) tw(HSTBL) tw(HSTBH) tsu(SELV-HASL) th(HASL-SELV) tsu(HDV-HSTBH) th(HSTBH-HDV) th(HRDYL-HSTBL) tsu(HASL-HSTBL) th(HSTBL-HASL) Setup time, select signals valid before HSTROBE low Hold time, select signals valid after HSTROBE low Pulse duration, HSTROBE low Pulse duration, HSTROBE high between consecutive accesses Setup time, select signals valid before HAS low Hold time, select signals valid after HAS low Setup time, host data valid before HSTROBE high Hold time, host data valid after HSTROBE high Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated until HRDY is active (low); otherwise, HPI writes will not complete properly. Setup time, HAS low before HSTROBE low -150 -225 MIN MAX UNIT
19 Hold time, HAS low after HSTROBE low HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. Select signals include: HCNTL[1:0], HR/W, and HHWIL.
switching characteristics over recommended operating conditions during host-port interface cycles (see Figure 40, Figure 41, Figure 42, and Figure 43)
NO. 5 6 7 8 9 15 16 17 td(HCS-HRDY) td(HSTBL-HRDYH) td(HSTBL-HDLZ) td(HDV-HRDYL) toh(HSTBH-HDV) td(HSTBH-HDHZ) td(HSTBL-HDV) td(HSTBH-HRDYH) td(HASL-HRDYH) PARAMETER Delay time, HCS to HRDY Delay time, HSTROBE low to HRDY high# Delay time, HSTROBE low to HD low impedance for an HPI read Delay time, HD valid to HRDY low Output hold time, HD valid after HSTROBE high Delay time, HSTROBE high to HD high impedance Delay time, HSTROBE low to HD valid Delay time, HSTROBE high to HRDY high|| -150 -225 MIN MAX UNIT
20 Delay time, HAS low to HRDY high HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy completing a previous HPID write or READ with autoincrement. # This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. || This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
HOST-PORT INTERFACE TIMING (CONTINUED)
HAS 1 HCNTL[1:0] 1 HR/W 1 HHWIL HSTROBE HCS 7 HD[15:0] (output) 5 1st halfword 8 2nd halfword 17 5 15 9 16 15 9 3 4 3 2 1 2 2 1 2 1 2 2
PRODUCT PREVIEW
HRDY (case 1) 6 8 17 5
HRDY (case 2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 40. HPI Read Timing (HAS Not Used, Tied High)
HAS 10 HCNTL[1:0] 11 10 HR/W 11 10 HHWIL HSTROBE HCS 7 HD[15:0] (output) 5 HRDY (case 1) 20 HRDY (case 2) For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 8 17 5 1st half-word 8 2nd half-word 17 5 18 15 9 16 9 3 4 18 15 10 11 10 11 19 11 10 19 11
Figure 41. HPI Read Timing (HAS Used)
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HOST-PORT INTERFACE TIMING (CONTINUED)
HAS 1 2 HCNTL[1:0] 1 HR/W 1 HHWIL 3 4 HSTROBE HCS 12 HD[15:0] (input) 5 HRDY HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 1st halfword 2nd halfword 17 5 13 12 13 14 3 2 1 2 2 1 2
1 2
Figure 42. HPI Write Timing (HAS Not Used, Tied High)
HAS 19 11 10 HCNTL[1:0] 11 10 HR/W 11 10 HHWIL 3 HSTROBE HCS HD[15:0] (input) 5 HRDY For correct operation, strobe the HAS signal only once per HSTROBE active cycle. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. 1st half-word 2nd half-word 17 5 18 12 13 14 4 18 12 13 10 11 10 11 10 19 11
Figure 43. HPI Write Timing (HAS Used)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP (see Figure 44)
NO. 2 3 5 6 7 8 tc(CKRX) tw(CKRX) tsu(FRH-CKRL) th(CKRL-FRH) tsu(DRV-CKRL) th(CKRL-DRV) tsu(FXH-CKXL) th(CKXL-FXH) Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Setup time external FSR high before CLKR low time, Hold time external FSR high after CLKR low time, Setup time DR valid before CLKR low time, Hold time DR valid after CLKR low time, Setup time external FSX high before CLKX low time, Hold time external FSX high after CLKX low time, CLKR/X ext CLKR/X ext CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKR int CLKR ext CLKX int 10 11 CLKX ext CLKX int CLKX ext CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. The minimum CLKR/X period is twice the CPU cycle time (2P). This means that the maximum bit rate for communications between the McBSP and other device is 75 Mbps for 150 MHz CPU clock or 50 Mbps for 100 MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 33 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 30 ns (33 MHz), whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 33 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. -150 -225 MIN MAX UNIT
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SPRS186 - DECEMBER 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP (see Figure 44)
NO. PARAMETER Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input Cycle time, CLKR/X Pulse duration, CLKR/X high or CLKR/X low Delay time, CLKR high to internal FSR valid Delay time CLKX high to internal FSX valid time, Disable time, DX high im edance following last data bit impedance from CLKX high Delay time CLKX high to DX valid time, Delay time, FSX high to DX valid 14 td(FXH-DXV) ONLY applies when in data delay 0 (XDATDLY = 00b) mode CLKR/X int CLKR/X int CLKR int CLKX int 9 12 13 td(CKXH-FXV) tdis(CKXH-DXHZ) td(CKXH-DXV) CLKX ext CLKX int CLKX ext CLKX int CLKX ext FSX int FSX ext -150 -225 MIN 1 2 3 4 td(CKSH-CKRXH) tc(CKRX) tw(CKRX) td(CKRH-FRV) MAX UNIT
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Minimum delay times also represent minimum output hold times. P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. The minimum CLKR/X period is twice the CPU cycle time (2P). This means that the maximum bit rate for communications between the McBSP and other device is 75 Mbps for 150 MHz CPU clock or 50 Mbps for 100 MHz CPU clock; where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 33 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 30 ns (33 MHz), whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 33 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P = 33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave. # C = H or L S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see footnote above). || Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. If DXENA = 0, then D1 = D2 = 0 If DXENA = 1, then D1 = 2P, D2 = 4P
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKS 1 3 3 CLKR 4 FSR (int) 5 FSR (ext) 7 DR 2 3 CLKX 9 3 Bit(n-1) 8 (n-2) (n-3) 6 4 2
PRODUCT PREVIEW
FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 12 DX Bit 0 14 13 Bit(n-1) 13 (n-2) (n-3)
Figure 44. McBSP Timings
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SPRS186 - DECEMBER 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 45)
NO. 1 2 tsu(FRH-CKSH) th(CKSH-FRH) Setup time, FSR high before CLKS high Hold time, FSR high after CLKS high -150 -225 MIN MAX UNIT
CLKS 1 FSR external CLKR/X (no need to resync) CLKR/X (needs resync) 2
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Figure 45. FSR Timing When GSYNC = 1
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 46)
-150 -225 NO NO. MASTER MIN 4 tsu(DRV-CKXL) th(CKXL-DRV) Setup time, DR valid before CLKX low MAX SLAVE MIN MAX UNIT
5 Hold time, DR valid after CLKX low P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 46)
-150 -225 NO. NO PARAMETER MASTER MIN 1 2 3 6 7 th(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) tdis(CKXL-DXHZ) tdis(FXH-DXHZ) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX low Disable time, DX high impedance following last data bit from FSX high MAX SLAVE MIN MAX UNIT
PRODUCT PREVIEW
8 td(FXL-DXV) Delay time, FSX low to DX valid P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
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SPRS186 - DECEMBER 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 3 Bit(n-1) 5 (n-2) (n-3) (n-4) (n-2) (n-3) (n-4) 2
Figure 46. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 47)
-150 -225 NO NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high MAX SLAVE MIN MAX UNIT
5 Hold time, DR valid after CLKX high P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 47)
-150 -225 NO. NO PARAMETER MASTER MIN 1 2 3 6 th(CKXL-FXL) td(FXL-CKXH) td(CKXL-DXV) tdis(CKXL-DXHZ) Hold time, FSX low after CLKX low Delay time, FSX low to CLKX high# Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX low MAX SLAVE MIN MAX UNIT
PRODUCT PREVIEW
7 td(FXL-DXV) Delay time, FSX low to DX valid P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
CLKX 1 FSX 6 Bit 0 7 Bit(n-1) 4 DR Bit 0 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
DX
Figure 47. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 48)
-150 -225 NO NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high MAX SLAVE MIN MAX UNIT
5 Hold time, DR valid after CLKX high P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 48)
-150 -225 NO. NO PARAMETER MASTER MIN 1 2 3 6 7 th(CKXH-FXL) td(FXL-CKXL) td(CKXL-DXV) tdis(CKXH-DXHZ) tdis(FXH-DXHZ) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# Delay time, CLKX low to DX valid Disable time, DX high impedance following last data bit from CLKX high Disable time, DX high impedance following last data bit from FSX high MAX SLAVE MIN MAX UNIT
8 td(FXL-DXV) Delay time, FSX low to DX valid P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX 1 FSX 7 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 8 Bit(n-1) 5 (n-2) (n-3) (n-4) 3 (n-2) (n-3) (n-4) 2
Figure 48. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
PRODUCT PREVIEW
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SPRS186 - DECEMBER 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 49)
-150 -225 NO NO. MASTER MIN 4 tsu(DRV-CKXH) th(CKXH-DRV) Setup time, DR valid before CLKX high MAX SLAVE MIN MAX UNIT
5 Hold time, DR valid after CLKX high P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 49)
-150 -225 NO. NO PARAMETER MASTER MIN 1 2 3 6 th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXHZ) Hold time, FSX low after CLKX high Delay time, FSX low to CLKX low# Delay time, CLKX high to DX valid Disable time, DX high impedance following last data bit from CLKX high MAX SLAVE MIN MAX UNIT
7 td(FXL-DXV) Delay time, FSX low to DX valid P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX).
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX 1 FSX 6 DX Bit 0 4 DR Bit 0 Bit(n-1) 7 Bit(n-1) 3 (n-2) 5 (n-2) (n-3) (n-4) (n-3) (n-4) 2
Figure 49. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
PRODUCT PREVIEW
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TIMER TIMING timing requirements for timer inputs (see Figure 50)
NO. 1 2 tw(TINPH) tw(TINPL) Pulse duration, TINP high -150 -225 MIN Pulse duration, TINP low P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. MAX UNIT
switching characteristics over recommended operating conditions for timer outputs (see Figure 50)
NO. 3 4 tw(TOUTH) tw(TOUTL) Pulse duration, TOUT high PARAMETER -150 -225 MIN Pulse duration, TOUT low P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. 2 1 TINPx 3 TOUTx 4 MAX UNIT
Figure 50. Timer Timing
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING timing requirements for GPIO inputs (see Figure 51)
NO. 1 2 tw(GPIH) tw(GPIL) Pulse duration, GPIx high -150 -225 MIN Pulse duration, GPIx low P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. MAX UNIT
switching characteristics over recommended operating conditions for GPIO outputs (see Figure 51)
NO. 3 tw(GPOH) tw(GPOL) Pulse duration, GPOx high PARAMETER -150 -225 MIN Pulse duration, GPOx low P = 1/CPU clock frequency in ns. For example, when running parts at 225 MHz, use P = 4.4 ns. 2 1 GPIx 3 GPOx 4 4 MAX UNIT
PRODUCT PREVIEW
Figure 51. GPIO Port Timing
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SPRS186 - DECEMBER 2001
JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 52)
NO. 1 3 4 tc(TCK) tsu(TDIV-TCKH) th(TCKH-TDIV) Cycle time, TCK Setup time, TDI/TMS/TRST valid before TCK high Hold time, TDI/TMS/TRST valid after TCK high -150 -225 MIN MAX UNIT
switching characteristics over recommended operating conditions for JTAG test port (see Figure 52)
NO. 2 td(TCKL-TDOV) PARAMETER Delay time, TCK low to TDO valid -150 -225 MIN MAX UNIT
1 TCK 2 TDO 4 3 TDI/TMS/TRST 2
Figure 52. JTAG Test-Port Timing
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
MECHANICAL DATA
GFN (S-PBGA-N256)
27,20 SQ 26,80 24,70 SQ 23,95 Y W V U T R P N M L K J H G F E D C B A 1 2 2,32 MAX 3 4 5 6 7 8 9 10 11 13 15 17 19 12 14 16 18 20
PLASTIC BALL GRID ARRAY
24,13 TYP 1,27 0,635
PRODUCT PREVIEW
1,17 NOM
Seating Plane 0,40 0,30 0,90 0,60 0,15 M 0,15
0,70 0,50
4040185-2/B 11/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
thermal resistance characteristics (S-PBGA package)
NO 1 2 3 4 5 RJC RJA RJA RJA Junction-to-case Junction-to-free air Junction-to-free air Junction-to-free air C/W Air Flow (m/s) N/A 0.0 0.5 1.0 2.0
RJA Junction-to-free air m/s = meters per second
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0,635
1,27
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
MECHANICAL DATA
PYP (S-PQFP-G208)
156 105
PowerPAD PLASTIC QUAD FLATPACK
157
104
Thermal Pad (See Note D)
0,27 0,17
0,08 M
0,50
0,13 NOM 208 53
1 25,50 TYP 28,05 SQ 27,95 30,10 SQ 29,90 1,45 1,35
52
Gage Plane 0,25 0,15 0,05 0,75 0,45 Seating Plane 0- 7
1,60 MAX
0,08
4146966/A 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SPRS186 - DECEMBER 2001
MECHANICAL DATA (CONTINUED) thermal resistance characteristics (S-PQFP-G208 package)
NO 1 2 3 4 5 RJC RJA RJA RJA Junction-to-case Junction-to-free air Junction-to-free air Junction-to-free air C/W Air Flow (m/s) N/A 0.0 0.5 1.0 2.0
RJA Junction-to-free air m/s = meters per second
PRODUCT PREVIEW
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